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    Method for forming offset spacers for semiconductor device arrangements
    1.
    发明授权
    Method for forming offset spacers for semiconductor device arrangements 有权
    用于形成用于半导体器件布置的偏置间隔物的方法

    公开(公告)号：US07767508B2

    公开(公告)日：2010-08-03

    申请号：US11580952

    申请日：2006-10-16

    申请人： Philip A. Fisher ,  Laura A. Brown ,  Johannes Groschopf ,  Huicai Zhong

    发明人： Philip A. Fisher ,  Laura A. Brown ,  Johannes Groschopf ,  Huicai Zhong

    IPC分类号： H01L21/338

    CPC分类号： H01L29/4983 ,  H01L21/31144 ,  H01L29/66659 ,  H01L29/66772

    摘要： Methods are provided for the fabrication of abrupt and tunable offset spacers for improved transistor short channel control. The methods include the formation of a gate electrode within a dielectric layer, with only a top portion of the gate electrode exposed. Silicon is added on the top portion of the gate electrode, by selective epitaxial growth, for example. Etching of the dielectric layer is performed with added silicon at the top portion of the gate electrode serving as a silicon mask to prevent etching of the dielectric layer directly underneath the silicon mask, which includes overhangs over the gate electrode sidewalls. The etching creates offset spacers in a production-worthy manner, and can be used to form offset spacers that are asymmetrical in width. By running the methodology in a microloading regime, wider offset spacers may be created on narrower polysilicon gate features, thereby improving Vt roll-off.

    摘要翻译： 提供了用于制造用于改善晶体管短沟道控制的突发和可调偏移间隔物的方法。 这些方法包括在电介质层内形成栅电极，仅露出栅电极的顶部。 例如，通过选择性外延生长将硅添加到栅电极的顶部。 介电层的蚀刻是在栅电极的顶部添加硅作为硅掩模进行的，以防止直接在硅掩模下面的电介质层的蚀刻，该掩模包括在栅电极侧壁上的突出端。 蚀刻以生产价值的方式产生偏移间隔物，并且可以用于形成不对称宽度的偏移间隔物。 通过在微加载方案中运行该方法，可以在较窄的多晶硅栅极特征上产生更宽的偏移间隔物，从而改善Vt滚降。

    Method for forming offset spacers for semiconductor device arrangements
    2.
    发明申请
    Method for forming offset spacers for semiconductor device arrangements 有权
    用于形成用于半导体器件布置的偏置间隔物的方法

    公开(公告)号：US20080090368A1

    公开(公告)日：2008-04-17

    申请号：US11580952

    申请日：2006-10-16

    申请人： Philip A. Fisher ,  Laura A. Brown ,  Johannes Groschopf ,  Huicai Zhong

    发明人： Philip A. Fisher ,  Laura A. Brown ,  Johannes Groschopf ,  Huicai Zhong

    IPC分类号： H01L21/336

    CPC分类号： H01L29/4983 ,  H01L21/31144 ,  H01L29/66659 ,  H01L29/66772

    摘要： Methods are provided for the fabrication of abrupt and tunable offset spacers for improved transistor short channel control. The methods include the formation of a gate electrode within a dielectric layer, with only a top portion of the gate electrode exposed. Silicon is added on the top portion of the gate electrode, by selective epitaxial growth, for example. Etching of the dielectric layer is performed with added silicon at the top portion of the gate electrode serving as a silicon mask to prevent etching of the dielectric layer directly underneath the silicon mask, which includes overhangs over the gate electrode sidewalls. The etching creates offset spacers in a production-worthy manner, and can be used to form offset spacers that are asymmetrical in width. By running the methodology in a microloading regime, wider offset spacers may be created on narrower polysilicon gate features, thereby improving Vt roll-off.

    摘要翻译： 提供了用于制造用于改善晶体管短沟道控制的突发和可调偏移间隔物的方法。 这些方法包括在电介质层内形成栅电极，仅露出栅电极的顶部。 例如，通过选择性外延生长将硅添加到栅电极的顶部。 介电层的蚀刻是在栅电极的顶部添加硅作为硅掩模进行的，以防止直接在硅掩模下面的电介质层的蚀刻，该掩模包括在栅电极侧壁上的突出端。 蚀刻以生产价值的方式产生偏移间隔物，并且可以用于形成不对称宽度的偏移间隔物。 通过在微加载方案中运行该方法，可以在较窄的多晶硅栅极特征上产生更宽的偏移间隔物，从而改善Vt滚降。

    Trench replacement gate process for transistors having elevated source and drain regions
    3.
    发明申请
    Trench replacement gate process for transistors having elevated source and drain regions 审中-公开
    具有升高的源极和漏极区域的晶体管的沟槽替换栅极工艺

    公开(公告)号：US20080070356A1

    公开(公告)日：2008-03-20

    申请号：US11520607

    申请日：2006-09-14

    申请人： Laura A. Brown ,  Philip A. Fisher ,  Huicai Zhong ,  Johannes Groschopf

    发明人： Laura A. Brown ,  Philip A. Fisher ,  Huicai Zhong ,  Johannes Groschopf

    IPC分类号： H01L21/336 ,  H01L21/8234

    CPC分类号： H01L29/41783 ,  H01L21/28114 ,  H01L21/823814 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66606

    摘要： The method for forming a semiconductor device arrangement with raised source/drains includes depositing a raised source/drain layer on a substrate, followed by a sacrificial layer on the raised source/drain layer. A trench is formed in the sacrificial layer and the raised source/drain layer, and sidewall spacers are formed within the trench. A replacement gate is formed between the sidewall spacers and the sacrificial layer is removed to expose the raised source/drain regions. The sidewall spacers may then be removed from the sidewalls of the replacement gate, leaving the replacement gate a defined distance from the raised source/drain regions.

    摘要翻译： 用于形成具有升高的源极/漏极的半导体器件布置的方法包括在衬底上沉积凸起的源极/漏极层，随后在凸起的源极/漏极层上沉积牺牲层。 在牺牲层和凸起的源极/漏极层中形成沟槽，并且在沟槽内形成侧壁间隔物。 在侧壁间隔件之间形成替换栅极，去除牺牲层以露出升高的源极/漏极区域。 然后可以从替换浇口的侧壁去除侧壁间隔物，使替换浇口与凸起的源极/漏极区域保持一定距离。

    Method of forming sub-lithographic spaces between polysilicon lines
    6.
    发明授权
    Method of forming sub-lithographic spaces between polysilicon lines 失效
    在多晶硅线之间形成次光刻空间的方法

    公开(公告)号：US06500756B1

    公开(公告)日：2002-12-31

    申请号：US10184251

    申请日：2002-06-28

    申请人： Scott A. Bell ,  Philip A. Fisher ,  Richard C. Nguyen ,  Cyrus E. Tabery

    发明人： Scott A. Bell ,  Philip A. Fisher ,  Richard C. Nguyen ,  Cyrus E. Tabery

    IPC分类号： H01L214763

    CPC分类号： H01L21/76816 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139

    摘要： A method of forming spaces between polysilicon lines can include patterning structures having top SiON layers and bottom amorphous carbon layers where the structures are located over a polysilicon layer and are separated by a first width, forming amorphous carbon spacers along lateral side walls of the patterned structures, etching apertures into the polysilicon layer not covered by the amorphous carbon spacers and the patterned structures where the apertures in the polysilicon layer between adjacent patterned structures have a second width, and ashing away the amorphous carbon spacers and the patterned structures. The second width is less than the first width.

    摘要翻译： 在多晶硅线之间形成空间的方法可以包括具有顶部SiON层和底部无定形碳层的图形结构，其中结构位于多晶硅层上方并且被第一宽度分开，从而沿图案化结构的侧壁形成非晶碳间隔物 蚀刻入未被无定形碳间隔物和图案化结构覆盖的多晶硅层中的孔，其中相邻图案化结构之间的多晶硅层中的孔具有第二宽度，并且将非晶碳间隔物和图案化结构灰化。 第二宽度小于第一宽度。

    Method and arrangement for reducing source/drain resistance with epitaxial growth
    9.
    发明授权
    Method and arrangement for reducing source/drain resistance with epitaxial growth 有权
    用外延生长降低源/漏电阻的方法和装置

    公开(公告)号：US07183169B1

    公开(公告)日：2007-02-27

    申请号：US11072312

    申请日：2005-03-07

    申请人： Andrew M. Waite ,  Scott Luning ,  Philip A. Fisher

    发明人： Andrew M. Waite ,  Scott Luning ,  Philip A. Fisher

    IPC分类号： H01L21/336

    CPC分类号： H01L29/78621 ,  H01L29/665 ,  H01L29/66628

    摘要： A method and arrangement for reducing the series resistance of the source and drain in a MOSFET device provides for epitaxially grown regions on top of the source and drain extensions to cover portions of the top surfaces of the silicide regions formed on the substrate. The epitaxial material provides an extra flow path for current to flow through to the silicide from the extension, as well as increasing the surface area between the source/drain and the silicide to reduce the contact resistance between the source/drain and the silicide.

    摘要翻译： 用于降低MOSFET器件中的源极和漏极的串联电阻的方法和装置提供了在源极和漏极延伸部的顶部上的外延生长区域，以覆盖形成在衬底上的硅化物区域的顶表面的部分。 外延材料提供了一个额外的流动路径，用于电流从延伸部分流到硅化物，以及增加源极/漏极和硅化物之间的表面积，以减少源极/漏极和硅化物之间的接触电阻。