公开(公告)号：US08779862B2

公开(公告)日：2014-07-15

申请号：US13550195

申请日：2012-07-16

Applicant: Prashant Dubey

Inventor： Prashant Dubey

IPC: H03K3/03 ,  H03B5/32 ,  H03B5/08 ,  H03L7/099

CPC classification number: H03K3/0315 ,  H03B5/08 ,  H03B5/32 ,  H03B2200/009 ,  H03L7/0995

Abstract: An oscillator having a plurality of operatively coupled ring oscillators arranged in hyper-matrix architecture. The operatively coupled ring oscillators are either identical or non-identical and are coupled through a common inverter or tail current transistors. Due to the arrangement of the ring oscillators in a hyper-matrix structure, the ring oscillators are synchronized and resist any variation in frequency or phase thereby maintaining a consistent phase noise performance.

Abstract translation: 具有以超矩阵结构排列的多个可操作耦合的环形振荡器的振荡器。 可操作耦合的环形振荡器是相同的或不相同的，并且通过公共的逆变器或尾电流晶体管耦合。 由于环形振荡器在超矩阵结构中的布置，环形振荡器被同步并抵抗频率或相位的任何变化，从而保持一致的相位噪声性能。

公开(公告)号：US08638175B2

公开(公告)日：2014-01-28

申请号：US13177460

申请日：2011-07-06

Applicant: Prashant Dubey

Inventor： Prashant Dubey

IPC: H03K3/03 ,  H03L7/24

CPC classification number: H03K3/0315

Abstract: A circuit including a first oscillator configured to oscillate at a first frequency; a second oscillator configured to oscillate at a second frequency, the second frequency being different from and one of a harmonic or sub-harmonic of the first frequency; and a coupling between the first oscillator and the second oscillator configured to injection lock at least one of the first oscillator and second oscillator to the other of the first oscillator and second oscillator.

Abstract translation: 一种包括配置成以第一频率振荡的第一振荡器的电路; 第二振荡器，其被配置为以第二频率振荡，所述第二频率不同于所述第一频率的谐波或次谐波; 以及第一振荡器和第二振荡器之间的耦合，被配置为将第一振荡器和第二振荡器中的至少一个注入锁定到第一振荡器和第二振荡器中的另一个。

公开(公告)号：US20120280756A1

公开(公告)日：2012-11-08

申请号：US13550195

申请日：2012-07-16

Applicant: Prashant Dubey

Inventor： Prashant Dubey

IPC: H03K3/03

CPC classification number: H03K3/0315 ,  H03B5/08 ,  H03B5/32 ,  H03B2200/009 ,  H03L7/0995

Abstract: An oscillator having a plurality of operatively coupled ring oscillators arranged in hyper-matrix architecture. The operatively coupled ring oscillators are either identical or non-identical and are coupled through a common inverter or tail current transistors. Due to the arrangement of the ring oscillators in a hyper-matrix structure, the ring oscillators are synchronized and resist any variation in frequency or phase thereby maintaining a consistent phase noise performance

Abstract translation: 具有以超矩阵结构排列的多个可操作耦合的环形振荡器的振荡器。 可操作耦合的环形振荡器是相同的或不相同的，并且通过公共的逆变器或尾电流晶体管耦合。 由于环形振荡器在超矩阵结构中的布置，环形振荡器被同步并抵抗频率或相位的任何变化，从而保持一致的相位噪声性能

公开(公告)号：US20120161883A1

公开(公告)日：2012-06-28

申请号：US13177460

申请日：2011-07-06

Applicant: Prashant Dubey

Inventor： Prashant Dubey

IPC: H03K3/03

CPC classification number: H03K3/0315

Abstract: A circuit including a first oscillator configured to oscillate at a first frequency; a second oscillator configured to oscillate at a second frequency, the second frequency being different from and one of a harmonic or sub-harmonic of the first frequency; and a coupling between the first oscillator and the second oscillator configured to injection lock at least one of the first oscillator and second oscillator to the other of the first oscillator and second oscillator.

Abstract translation: 一种包括配置成以第一频率振荡的第一振荡器的电路; 第二振荡器，其被配置为以第二频率振荡，所述第二频率不同于所述第一频率的谐波或次谐波; 以及第一振荡器和第二振荡器之间的耦合，被配置为将第一振荡器和第二振荡器中的至少一个注入锁定到第一振荡器和第二振荡器中的另一个。

公开(公告)号：US08046655B2

公开(公告)日：2011-10-25

申请号：US11437420

申请日：2006-05-18

Applicant: Prashant Dubey

Inventor： Prashant Dubey

IPC: G01R31/28 ,  G06F11/00

CPC classification number: G11C29/02 ,  G11C5/025 ,  G11C29/024 ,  G11C2029/1206

Abstract: An integrated test device reduces external wiring congestion to a memory. The integrated test device provides for separate decoder testing and debugging to find specific errors in the memory. The device also helps in reducing the complexity of the test of external BIST. Furthermore, the number of clock cycles required for the decoder testing for an N-address memory is reduced from 4N cycles to N clock cycles. Additionally, the access time for the memory is reduced as the test device is used as a pipelining device in normal operation mode.

Abstract translation: 集成的测试设备减少了存储器的外部布线拥塞。 集成测试设备提供单独的解码器测试和调试来查找存储器中的特定错误。 该器件还有助于降低外部BIST测试的复杂性。 此外，N寻址存储器的解码器测试所需的时钟周期数从4N周期减少到N个时钟周期。 此外，随着测试设备在正常操作模式下用作流水线设备，存储器的访问时间减少。

公开(公告)号：US08624623B2

公开(公告)日：2014-01-07

申请号：US13340674

申请日：2011-12-30

Applicant: Navneet Gupta ,  Prashant Dubey ,  Kaushik Saha ,  AtulKumar Kashyap

Inventor： Navneet Gupta ,  Prashant Dubey ,  Kaushik Saha ,  AtulKumar Kashyap

IPC: H03K19/003 ,  H03K19/173

CPC classification number: H03K3/356156 ,  H03K3/0375

Abstract: According to an embodiment, an apparatus includes: a first node configured to receive a data input signal of a data latch; a second node configured to receive a data output signal of the data latch; process and hold circuitry configured to process a difference between a value of the data input signal received at the first node and a value of the data output signal received at the second node and hold respective values at the first and second nodes responsive to the difference; and comparison circuitry configured to compare the value held at the first node and a value of the data output signal of the data latch; wherein the process and hold circuitry is configured to be biased toward the signal received at one of the first node and the second node.

Abstract translation: 根据实施例，一种装置包括：被配置为接收数据锁存器的数据输入信号的第一节点; 第二节点，被配置为接收数据锁存器的数据输出信号; 处理和保持电路，被配置为处理在第一节点处接收的数据输入信号的值与在第二节点处接收到的数据输出信号的值之间的差异，并响应于该差异保持第一和第二节点处的相应值; 以及比较电路，被配置为比较在第一节点处保持的值和数据锁存器的数据输出信号的值; 其中所述处理和保持电路被配置为朝向在所述第一节点和所述第二节点之一处接收的信号偏置。

公开(公告)号：US08232843B2

公开(公告)日：2012-07-31

申请号：US12644984

申请日：2009-12-22

Applicant: Prashant Dubey

Inventor： Prashant Dubey

IPC: H03L7/07 ,  H03K3/03

CPC classification number: H03K3/0315 ,  H03B5/08 ,  H03B5/32 ,  H03B2200/009 ,  H03L7/0995

Abstract: An oscillator having a plurality of operatively coupled ring oscillators arranged in hyper-matrix architecture. The operatively coupled ring oscillators are either identical or non-identical and are coupled through a common inverter or tail current transistors. Due to the arrangement of the ring oscillators in a hyper-matrix structure, the ring oscillators are synchronized and resist any variation in frequency or phase thereby maintaining a consistent phase noise performance

Abstract translation: 具有以超矩阵结构排列的多个可操作耦合的环形振荡器的振荡器。 可操作耦合的环形振荡器是相同的或不相同的，并且通过公共的逆变器或尾电流晶体管耦合。 由于环形振荡器在超矩阵结构中的布置，环形振荡器被同步并抵抗频率或相位的任何变化，从而保持一致的相位噪声性能

公开(公告)号：US08108744B2

公开(公告)日：2012-01-31

申请号：US11891848

申请日：2007-08-13

Applicant: Prashant Dubey ,  Akhil Garg ,  Sravan Kumar Bhaskarani

Inventor： Prashant Dubey ,  Akhil Garg ,  Sravan Kumar Bhaskarani

IPC: G11C29/00 ,  G01R31/28

CPC classification number: G11C29/16 ,  G11C29/1201 ,  G11C29/26 ,  G11C29/32 ,  G11C2029/0401 ,  G11C2029/2602 ,  G11C2029/5602

Abstract: A system and method of sharing testing components for multiple embedded memories and the memory system incorporating the same. The memory system includes multiple test controllers, multiple interface devices, a main controller, and a serial interface. The main controller is used for initializing testing of each of the dissimilar memory groups using a serial interface and local test controllers. The memory system results in reduced routing congestion and faster testing of plurality of dissimilar memories. The present disclosure further provides a programmable shared built in self testing (BIST) architecture utilizing globally asynchronous and locally synchronous (GALS) methodology for testing multiple memories. The built in self test (BIST) architecture includes a programmable master controller, multiple memory wrappers, and an interface. The interface can be a globally asynchronous and locally synchronous (GALS) interface.

Abstract translation: 一种共享用于多个嵌入式存储器的测试组件的系统和方法以及包含其的存储器系统。 存储系统包括多个测试控制器，多个接口设备，主控制器和串行接口。 主控制器用于使用串行接口和本地测试控制器初始化每个不同内存组的测试。 存储器系统导致路由拥塞减少和多个不同存储器的更快测试。 本公开还提供了一种使用全局异步和本地同步（GALS）方法来测试多个存储器的可编程共享内建自测试（BIST）架构。 内置自检（BIST）架构包括可编程主控制器，多个存储器包装器和接口。 该接口可以是全局异步和本地同步（GALS）接口。

公开(公告)号：US07496809B2

公开(公告)日：2009-02-24

申请号：US11423393

申请日：2006-06-09

Applicant: Prashant Dubey

Inventor： Prashant Dubey

IPC: G11C29/00

CPC classification number: G01R31/318533 ,  G11C29/02 ,  G11C29/022 ,  G11C29/1201 ,  G11C29/48 ,  G11C29/50012 ,  G11C2029/0401 ,  G11C2029/3202

Abstract: An integrated scannable interface for testing memory. The interface includes a selection device for selecting a signal from at least two input signals responsive to an activation signal, a first storage device coupled to the output of the selection device for storing the signal responsive to a first enable signal and generating an output signal for the memory. The first storage device is connected at the input node of the memory, and a second storage device is coupled at its input to the first storage device for storing the output signal responsive to a second enable signal and generating a test signal for testing the memory. The output signal is observed for debugging faults between the integrated scannable interface and the memory and for debugging faults between the first and second storage devices.

Abstract translation: 用于测试内存的集成可扫描接口。 该接口包括用于响应于激活信号从至少两个输入信号中选择信号的选择装置，耦合到选择装置的输出的第一存储装置，用于响应于第一使能信号存储信号并产生输出信号 记忆。 第一存储装置连接在存储器的输入节点处，第二存储装置在其输入处耦合到第一存储装置，用于响应于第二使能信号存储输出信号，并产生用于测试存储器的测试信号。 观察输出信号用于集成可扫描接口和存储器之间的调试故障，并用于调试第一和第二存储设备之间的故障。

公开(公告)号：US20080126892A1

公开(公告)日：2008-05-29

申请号：US11891848

申请日：2007-08-13

Applicant: Prashant Dubey ,  Akhil Garg ,  Sravan Kumar Bhaskarani

Inventor： Prashant Dubey ,  Akhil Garg ,  Sravan Kumar Bhaskarani

IPC: G11C29/00 ,  G01R31/28

CPC classification number: G11C29/16 ,  G11C29/1201 ,  G11C29/26 ,  G11C29/32 ,  G11C2029/0401 ,  G11C2029/2602 ,  G11C2029/5602

Abstract: A system and method of sharing testing components for multiple embedded memories and the memory system incorporating the same. The memory system includes multiple test controllers, multiple interface devices, a main controller, and a serial interface. The main controller is used for initializing testing of each of the dissimilar memory groups using a serial interface and local test controllers. The memory system results in reduced routing congestion and faster testing of plurality of dissimilar memories. The present disclosure further provides a programmable shared built in self testing (BIST) architecture utilizing globally asynchronous and locally synchronous (GALS) methodology for testing multiple memories. The built in self test (BIST) architecture includes a programmable master controller, multiple memory wrappers, and an interface. The interface can be a globally asynchronous and locally synchronous (GALS) interface.

Abstract translation: 一种共享用于多个嵌入式存储器的测试组件的系统和方法以及包含其的存储器系统。 存储系统包括多个测试控制器，多个接口设备，主控制器和串行接口。 主控制器用于使用串行接口和本地测试控制器初始化每个不同内存组的测试。 存储器系统导致路由拥塞减少和多个不同存储器的更快测试。 本公开还提供了一种使用全局异步和本地同步（GALS）方法来测试多个存储器的可编程共享内建自测试（BIST）架构。 内置自检（BIST）架构包括可编程主控制器，多个存储器包装器和接口。 该接口可以是全局异步和本地同步（GALS）接口。