公开(公告)号：US08386864B2

公开(公告)日：2013-02-26

申请号：US13361749

申请日：2012-01-30

Applicant: Prashant Dubey ,  Akhil Garg ,  Sravan Kumar Bhaskarani

Inventor： Prashant Dubey ,  Akhil Garg ,  Sravan Kumar Bhaskarani

IPC: G01R31/28

CPC classification number: G11C29/16 ,  G11C29/1201 ,  G11C29/26 ,  G11C29/32 ,  G11C2029/0401 ,  G11C2029/2602 ,  G11C2029/5602

Abstract: A system and method of sharing testing components for multiple embedded memories and the memory system incorporating the same are disclosed. The memory system includes multiple test controllers, multiple interface devices, a main controller, and a serial interface. The main controller is used for initializing testing of each of the dissimilar memory groups using a serial interface and local test controllers. The memory system results in reduced routing congestion and faster testing of plurality of dissimilar memories. The present disclosure further provides a programmable shared built in self-testing (BIST) architecture utilizing globally asynchronous and locally synchronous (GALS) methodology for testing multiple memories. The built in self-test (BIST) architecture includes a programmable master controller, multiple memory wrappers, and an interface. The interface can be a globally asynchronous and locally synchronous (GALS) interface.

Abstract translation: 公开了一种共享用于多个嵌入式存储器的测试组件的系统和方法以及包含该测试组件的存储器系统。 存储系统包括多个测试控制器，多个接口设备，主控制器和串行接口。 主控制器用于使用串行接口和本地测试控制器初始化每个不同内存组的测试。 存储器系统导致路由拥塞减少和多个不同存储器的更快测试。 本公开还提供了一种利用全局异步和本地同步（GALS）方法来测试多个存储器的可编程共享的内建自测试（BIST）架构。 内置自检（BIST）架构包括可编程主控制器，多个存储器包装器和接口。 该接口可以是全局异步和本地同步（GALS）接口。

公开(公告)号：US08352781B2

公开(公告)日：2013-01-08

申请号：US12498143

申请日：2009-07-06

Applicant: Akhil Garg ,  Prashant Dubey

Inventor： Akhil Garg ,  Prashant Dubey

IPC: G06F11/16

CPC classification number: G11C29/4401 ,  G06F11/1048 ,  G11C29/42 ,  G11C29/46 ,  G11C29/70 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: The system and method are for efficient detection and restoration of data storage array defects. The system may include a data storage subsystem, wherein the data storage subsystem includes a data storage array, read-write logic coupled to the data storage array, a parity generator for producing and storing check data during write operations to the data storage array and generating check data during read operations on the data storage array, and a parity checker for verifying the stored check data with generated check data and identifying defective data read-write elements during read operations on the data storage array. The subsystem may further include a Built-in Self Test (BIST) generator operating only on the identified defective data read-write elements for determining defective data storage elements in the defective data read-write elements, and a restoration mechanism for restoring the valid operation of data access elements containing the defective data storage elements in the data storage array.

Abstract translation: 该系统和方法用于数据存储阵列缺陷的有效检测和恢复。 所述系统可以包括数据存储子系统，其中所述数据存储子系统包括数据存储阵列，耦合到所述数据存储阵列的读写逻辑，奇偶校验发生器，用于在对所述数据存储阵列的写操作期间产生和存储校验数据，并产生 在数据存储阵列的读取操作期间检查数据，以及奇偶校验器，用于利用生成的校验数据验证所存储的校验数据，并在数据存储阵列的读取操作期间识别缺陷数据读写元件。 该子系统可进一步包括内置自检（BIST）发生器，其操作仅用于识别缺陷数据读写元件中的有缺陷数据存储元件的缺陷数据读写元件，以及用于恢复有效操作的恢复机构 包含数据存储阵列中的有缺陷的数据存储元件的数据访问元件。

公开(公告)号：US08055956B2

公开(公告)日：2011-11-08

申请号：US11474121

申请日：2006-06-23

Applicant: Prashant Dubey ,  Amit Kashyap

Inventor： Prashant Dubey ,  Amit Kashyap

IPC: G11C29/00

CPC classification number: G11C29/802 ,  G11C29/4401 ,  G11C29/812

Abstract: The present invention provides a built-in self-repairable memory. The invention repairs a faulty IC through hard fuses, as well as through available redundancy in memories on chip. As the faults are not present in all the memories, the invention uses a lesser number of fuses to actually make a repair and thus results in a yield enhancement. The fuse data is stored in a compressed form and then decompressed as a restore happens at the power on. The fuse data interface with the memory to be repaired is serial. The serial links decreases the routing congestion and hence gain in area as well as gain in yield (due to lesser defects and reduced area).

Abstract translation: 本发明提供了一种内置的可自我修复的存储器。 本发明通过硬保险丝以及片上存储器中的可用冗余来修复故障IC。 由于故障不存在于所有存储器中，本发明使用较少数量的保险丝来实际进行修理，从而导致产量提高。 熔丝数据以压缩形式存储，然后在上电时恢复发生解压缩。 与要修复的存储器的保险丝数据接口是串行的。 串行链路减少路由拥塞，从而减少区域内的增益以及收益增益（由于较小的缺陷和减少的区域）。

公开(公告)号：US20100017651A1

公开(公告)日：2010-01-21

申请号：US12498143

申请日：2009-07-06

Applicant: Akhil Garg ,  Prashant Dubey

Inventor： Akhil Garg ,  Prashant Dubey

IPC: G06F11/00 ,  G06F11/08

CPC classification number: G11C29/4401 ,  G06F11/1048 ,  G11C29/42 ,  G11C29/46 ,  G11C29/70 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: The system and method are for efficient detection and restoration of data storage array defects. The system may include a data storage subsystem, wherein the data storage subsystem includes a data storage array, read-write logic coupled to the data storage array, a parity generator for producing and storing check data during write operations to the data storage array and generating check data during read operations on the data storage array, and a parity checker for verifying the stored check data with generated check data and identifying defective data read-write elements during read operations on the data storage array. The subsystem may further include a Built-in Self Test (BIST) generator operating only on the identified defective data read-write elements for determining defective data storage elements in the defective data read-write elements, and a restoration mechanism for restoring the valid operation of data access elements containing the defective data storage elements in the data storage array.

Abstract translation: 该系统和方法用于数据存储阵列缺陷的有效检测和恢复。 所述系统可以包括数据存储子系统，其中所述数据存储子系统包括数据存储阵列，耦合到所述数据存储阵列的读写逻辑，奇偶校验发生器，用于在对所述数据存储阵列的写入操作期间产生和存储校验数据并产生 在数据存储阵列的读取操作期间检查数据，以及奇偶校验器，用于利用生成的校验数据验证所存储的校验数据，并在数据存储阵列的读取操作期间识别缺陷数据读写元件。 该子系统可进一步包括内置自检（BIST）发生器，其操作仅用于识别缺陷数据读写元件中的有缺陷数据存储元件的缺陷数据读写元件，以及用于恢复有效操作的恢复机构 包含数据存储阵列中的有缺陷的数据存储元件的数据访问元件。

公开(公告)号：US07385862B2

公开(公告)日：2008-06-10

申请号：US11460071

申请日：2006-07-26

Applicant: Prashant Dubey

Inventor： Prashant Dubey

IPC: G11C7/00

CPC classification number: G11C29/808 ,  G11C29/846

Abstract: A memory system incorporates shared redundant memories and has a shared redundant memory architecture. The memory system includes a modified memory to be used as a shared redundant memory between memory systems. These memory systems may have several smaller memories forming a single logical memory or various memories in close proximity on an integrated circuit system. The shared redundancy is achieved by adding a comparator to the redundant element for comparing between the faulty address and the system address and performing a memory operation based on the comparator output. As the redundant memory operations are performed in parallel to the memory structures, setup and hold times are reduced. Shared redundancy also results in reduced integrated circuit area.

Abstract translation: 存储器系统包含共享冗余存储器并且具有共享冗余存储器架构。 存储器系统包括被修改的存储器，用作存储器系统之间的共享冗余存储器。 这些存储器系统可以具有形成单个逻辑存储器的几个更小的存储器或者在集成电路系统上非常接近的各种存储器。 通过向冗余元件添加比较器来实现共享冗余，以便在故障地址和系统地址之间进行比较，并且基于比较器输出执行存储器操作。 随着与存储器结构并行执行冗余存储器操作，减少了建立和保持时间。 共享冗余也导致集成电路面积减少。

公开(公告)号：US20070002649A1

公开(公告)日：2007-01-04

申请号：US11437420

申请日：2006-05-18

Applicant: Prashant Dubey

Inventor： Prashant Dubey

IPC: G11C29/00

CPC classification number: G11C29/02 ,  G11C5/025 ,  G11C29/024 ,  G11C2029/1206

Abstract: An integrated test device reduces external wiring congestion to a memory. The integrated test device provides for separate decoder testing and debugging to find specific errors in the memory. The device also helps in reducing the complexity of the test of external BIST. Furthermore, the number of clock cycles required for the decoder testing for an N-address memory is reduced from 4N cycles to N clock cycles. Additionally, the access time for the memory is reduced as the test device is used as a pipelining device in normal operation mode.

Abstract translation: 集成的测试设备减少了存储器的外部布线拥塞。 集成测试设备提供单独的解码器测试和调试来查找存储器中的特定错误。 该器件还有助于降低外部BIST测试的复杂性。 此外，N寻址存储器的解码器测试所需的时钟周期数从4N周期减少到N个时钟周期。 此外，随着测试设备在正常操作模式下用作流水线设备，存储器的访问时间减少。

公开(公告)号：US08737144B2

公开(公告)日：2014-05-27

申请号：US13340670

申请日：2011-12-29

Applicant: Navneet Gupta ,  Prashant Dubey ,  ShaileshKumar Pathak ,  Kaushik Saha ,  Ashish Kumar ,  R Sai Krishna

Inventor： Navneet Gupta ,  Prashant Dubey ,  ShaileshKumar Pathak ,  Kaushik Saha ,  Ashish Kumar ,  R Sai Krishna

IPC: G11C7/00

CPC classification number: G11C7/08 ,  G11C7/227

Abstract: An embodiment of a sense amplifier includes a sense circuit and a monitor circuit. The sense circuit is configured to convert a first signal that corresponds to data stored in a memory cell into a second signal that corresponds to the data, and the monitor circuit is configured to indicate a reliability of the second signal. The monitor circuit allows, for example, adjusting a parameter of a memory in which the memory cell is disposed to increase the read accuracy, and may also allow recognizing and correcting an error due to an invalid second signal.

Abstract translation: 读出放大器的实施例包括检测电路和监视电路。 感测电路被配置为将对应于存储在存储单元中的数据的第一信号转换成对应于数据的第二信号，并且监视电路被配置为指示第二信号的可靠性。 监视电路例如可以调整其中设置存储单元的存储器的参数以增加读取精度，并且还可以允许识别和校正由于无效的第二信号引起的错误。

公开(公告)号：US20120169378A1

公开(公告)日：2012-07-05

申请号：US13118858

申请日：2011-05-31

Applicant: Prashant Dubey ,  Navneet Gupta ,  Shailesh Kumar Pathak ,  Kaushik Saha ,  Gagandeep Singh Sachdev

Inventor： Prashant Dubey ,  Navneet Gupta ,  Shailesh Kumar Pathak ,  Kaushik Saha ,  Gagandeep Singh Sachdev

IPC: G01R19/00 ,  H03K5/00

CPC classification number: G11C7/065 ,  H04L25/0274

Abstract: A first sensing circuit has input terminals coupled to a true differential signal line and a complementary differential signal line. A second sensing circuit also has input terminals coupled to said true signal and said complementary signal. Each sensing circuit has a true signal sensing path and a complementary signal sensing path. The first sensing circuit has an imbalance that is biased towards the complementary signal sensing path, while the second sensing circuit has an imbalance that is biased towards the true signal sensing path. Outputs from the first and second sensing circuits are processed by a logic circuit producing an output signal that is indicative of whether there a sufficient differential signal for sensing has been developed between the true differential signal line and the complementary differential signal line.

Abstract translation: 第一感测电路具有耦合到真实差分信号线和互补差分信号线的输入端。 第二感测电路还具有耦合到所述真实信号和所述互补信号的输入端子。 每个感测电路具有真实的信号感测路径和互补信号感测路径。 第一感测电路具有偏置于互补信号感测路径的不平衡，而第二感测电路具有被偏置到真实信号感测路径的不平衡。 来自第一和第二感测电路的输出由逻辑电路处理，该逻辑电路产生一个输出信号，该输出信号指示在真实差分信号线和互补差分信号线之间是否存在足够的用于感测的差分信号。

公开(公告)号：US07248066B2

公开(公告)日：2007-07-24

申请号：US11025854

申请日：2004-12-29

Applicant: Ruchir Saraswat ,  Balwant Singh ,  Prashant Dubey

Inventor： Ruchir Saraswat ,  Balwant Singh ,  Prashant Dubey

IPC: G01R31/28 ,  G01R27/28 ,  G01R19/00

CPC classification number: G01R31/2884 ,  G01R31/3004

Abstract: An apparatus for enabling the on-chip analysis of the voltage and/or current transition behaviour of one or more embedded nets of an integrated circuit independently of the fabrication process. The said apparatus comprises a Reference Step Generator (RSG) for providing programmable reference voltages or currents, a Step Delay Generator (SDG) for providing programmable delays, a Comparator (C) that receives the output of the reference step generator on one input, the output from the node under test at the second input, and a latch enable signal from the step delay generator, and provides a latched digital output in response to the comparison, and a controller that co-ordinates the operation of the reference step generator, Step Delay Generator and Latching Comparator to provide a transient response measurement.

Abstract translation: 一种用于独立于制造过程实现片上分析集成电路的一个或多个嵌入网络的电压和/或电流转换特性的装置。 所述装置包括用于提供可编程参考电压或电流的参考步长发生器（RSG），用于提供可编程延迟的步进延迟发生器（SDG）;在一个输入端接收参考步进发生器的输出的比较器（C） 在来自第二输入的被测节点的输出以及来自阶梯延迟发生器的锁存使能信号，并且响应于该比较而提供锁存的数字输出;以及控制器，其对参考步长发生器的操作进行调节，步骤 延迟发生器和锁存比较器提供瞬态响应测量。

公开(公告)号：US08456197B2

公开(公告)日：2013-06-04

申请号：US13118858

申请日：2011-05-31

Applicant: Prashant Dubey ,  Navneet Gupta ,  Shailesh Kumar Pathak ,  Kaushik Saha ,  Gagandeep Singh Sachdev

Inventor： Prashant Dubey ,  Navneet Gupta ,  Shailesh Kumar Pathak ,  Kaushik Saha ,  Gagandeep Singh Sachdev

IPC: G01R19/00 ,  G11C7/00 ,  H03F3/45

CPC classification number: G11C7/065 ,  H04L25/0274

Abstract: A first sensing circuit has input terminals coupled to a true differential signal line and a complementary differential signal line. A second sensing circuit also has input terminals coupled to said true signal and said complementary signal. Each sensing circuit has a true signal sensing path and a complementary signal sensing path. The first sensing circuit has an imbalance that is biased towards the complementary signal sensing path, while the second sensing circuit has an imbalance that is biased towards the true signal sensing path. Outputs from the first and second sensing circuits are processed by a logic circuit producing an output signal that is indicative of whether there a sufficient differential signal for sensing has been developed between the true differential signal line and the complementary differential signal line.

Abstract translation: 第一感测电路具有耦合到真实差分信号线和互补差分信号线的输入端。 第二感测电路还具有耦合到所述真实信号和所述互补信号的输入端子。 每个感测电路具有真实的信号感测路径和互补信号感测路径。 第一感测电路具有偏置于互补信号感测路径的不平衡，而第二感测电路具有被偏置到真实信号感测路径的不平衡。 来自第一和第二感测电路的输出由逻辑电路处理，该逻辑电路产生一个输出信号，该输出信号指示在真实差分信号线和互补差分信号线之间是否存在足够的用于感测的差分信号。