公开(公告)号：US20190057757A1

公开(公告)日：2019-02-21

申请号：US16165549

申请日：2018-10-19

Applicant: QUALCOMM Incorporated

Inventor： Francois Ibrahim Atallah ,  Keith Alan Bowman ,  David Joseph Winston Hansquine ,  Jihoon Jeong ,  Hoan Huu Nguyen

IPC: G11C29/52 ,  G11C11/418 ,  G11C11/412 ,  H01L27/11 ,  G11C11/00 ,  G11C11/419

CPC classification number: G11C29/52 ,  G11C11/00 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419 ,  H01L27/11 ,  H01L27/1104

Abstract: Read-assist circuits for memory bit cells employing a P-type Field-Effect Transistor (PFET) read port(s) are disclosed. Related memory systems and methods are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type FET (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide memory bit cells having PFET read ports, as opposed to NFET read ports, to increase memory read times to the memory bit cells, and thus improve memory read performance. To mitigate or avoid a read disturb condition that could otherwise occur when reading the memory bit cell, read-assist circuits are provided for memory bit cells having PFET read ports.

公开(公告)号：US10115481B2

公开(公告)日：2018-10-30

申请号：US15645355

申请日：2017-07-10

Applicant: QUALCOMM Incorporated

Inventor： Francois Ibrahim Atallah ,  Keith Alan Bowman ,  David Joseph Winston Hansquine ,  Jihoon Jeong ,  Hoan Huu Nguyen

IPC: G11C29/52 ,  G11C11/418 ,  G11C11/412 ,  G11C11/419 ,  G11C11/00 ,  H01L27/11

Abstract: Read-assist circuits for memory bit cells employing a P-type Field-Effect Transistor (PFET) read port(s) are disclosed. Related memory systems and methods are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type FET (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide memory bit cells having PFET read ports, as opposed to NFET read ports, to increase memory read times to the memory bit cells, and thus improve memory read performance. To mitigate or avoid a read disturb condition that could otherwise occur when reading the memory bit cell, read-assist circuits are provided for memory bit cells having PFET read ports.

公开(公告)号：US09947406B2

公开(公告)日：2018-04-17

申请号：US14860844

申请日：2015-09-22

Applicant: QUALCOMM Incorporated

Inventor： Keith Alan Bowman ,  Francois Ibrahim Atallah ,  David Joseph Winston Hansquine ,  Jihoon Jeong ,  Hoan Huu Nguyen

IPC: G11C15/04 ,  G11C11/40 ,  H03K19/003 ,  H03K19/094

CPC classification number: G11C15/04 ,  G11C11/40 ,  H03K19/00315 ,  H03K19/094

Abstract: Dynamic tag compare circuits employing P-type Field-Effect Transistor (PFET)-dominant evaluation circuits for reduced evaluation time, and thus increased circuit performance, are provided. A dynamic tag compare circuit may be used or provided as part of searchable memory, such as a register file or content-addressable memory (CAM), as non-limiting examples. The dynamic tag compare circuit includes one or more PFET-dominant evaluation circuits comprised of one or more PFETs used as logic to perform a compare logic function. The PFET-dominant evaluation circuits are configured to receive and compare input search data to a tag(s) (e.g., addresses or data) contained in a searchable memory to determine if the input search data is contained in the memory. The PFET-dominant evaluation circuits are configured to control the voltage/value on a dynamic node in the dynamic tag compare circuit based on the evaluation of whether the received input search data is contained in the searchable memory.

公开(公告)号：US20160247559A1

公开(公告)日：2016-08-25

申请号：US14862712

申请日：2015-09-23

Applicant: QUALCOMM Incorporated

Inventor： Francois Ibrahim Atallah ,  Keith Alan Bowman ,  David Joseph Winston Hansquine ,  Jihoon Jeong ,  Hoan Huu Nguyen

IPC: G11C11/419

CPC classification number: G11C29/52 ,  G11C11/00 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419 ,  H01L27/11 ,  H01L27/1104

Abstract: Read-assist circuits for memory bit cells employing a P-type Field-Effect Transistor (PFET) read port(s) are disclosed. Related memory systems and methods are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type FET (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide memory bit cells having PFET read ports, as opposed to NFET read ports, to increase memory read times to the memory bit cells, and thus improve memory read performance. To mitigate or avoid a read disturb condition that could otherwise occur when reading the memory bit cell, read-assist circuits are provided for memory bit cells having PFET read ports.

Abstract translation: 公开了采用P型场效应晶体管（PFET）读端口的存储位单元的读辅助电路。 还公开了相关的存储器系统和方法。 已经观察到，随着节点技术的尺寸缩小，PFET驱动电流（即，驱动强度）超过用于相似尺寸的FET的N型FET（NFET）驱动电流。 在这方面，在一方面，期望提供与NFET读取端口相反的具有PFET读取端口的存储器位单元，以将存储器读取时间增加到存储器位单元，从而提高存储器读取性能。 为了减轻或避免在读取存储器位单元时可能发生的读取干扰条件，为具有PFET读取端口的存储器单元提供读取辅助电路。

公开(公告)号：US11270761B2

公开(公告)日：2022-03-08

申请号：US17223764

申请日：2021-04-06

Applicant: Qualcomm Incorporated

Inventor： Hoan Huu Nguyen ,  Francois Ibrahim Atallah ,  Keith Alan Bowman ,  Daniel Yingling ,  Jihoon Jeong ,  Yu Pu

IPC: G11C11/417 ,  G11C7/06 ,  G11C7/10 ,  G11C7/22 ,  G11C11/418 ,  G11C11/419

Abstract: A dual-mode memory is provided that includes a self-timed clock circuit for asserting a sense enable signal for a sense amplifier. In a low-bandwidth read mode, the self-timed clock circuit asserts the sense enable signal only once during a memory clock cycle. The sense amplifier then senses only a single bit from a group of multiplexed columns. In a high-bandwidth read mode, the self-timed clock circuit successively asserts the sense enable signal so that the sense amplifier successively senses bits from the multiplexed columns.

公开(公告)号：US10978139B2

公开(公告)日：2021-04-13

申请号：US16431503

申请日：2019-06-04

Applicant: QUALCOMM Incorporated

Inventor： Hoan Huu Nguyen ,  Francois Ibrahim Atallah ,  Keith Alan Bowman ,  Daniel Yingling ,  Jihoon Jeong ,  Yu Pu

IPC: G11C7/06 ,  G11C7/22 ,  G11C7/10 ,  G11C11/417 ,  G11C11/419 ,  G11C11/418

Abstract: A dual-mode memory is provided that includes a self-timed clock circuit for asserting a sense enable signal for a sense amplifier. In a low-bandwidth read mode, the self-timed clock circuit asserts the sense enable signal only once during a memory clock cycle. The sense amplifier then senses only a single bit from a group of multiplexed columns. In a high-bandwidth read mode, the self-timed clock circuit successively asserts the sense enable signal so that the sense amplifier successively senses bits from the multiplexed columns.

公开(公告)号：US10658029B2

公开(公告)日：2020-05-19

申请号：US16138174

申请日：2018-09-21

Applicant: QUALCOMM Incorporated

Inventor： Hoan Huu Nguyen ,  Francois Ibrahim Atallah ,  Keith Alan Bowman ,  Hari Rao

IPC: G11C11/4091 ,  G11C7/06 ,  G11C11/419 ,  G11C11/408 ,  G11C8/08 ,  G11C8/10 ,  G11C16/26

Abstract: Certain aspects of the present disclosure provide apparatus and methods for performing memory read operations. One example method generally includes precharging a plurality of memory columns during a precharging phase of a read access cycle. The method also includes sensing first data stored in a first memory cell of a first memory column of the plurality of memory columns during a memory read phase of the read access cycle, and sensing second data stored in a second memory cell of a second memory column of the plurality of memory columns during the same memory read phase of the read access cycle.

公开(公告)号：US10224084B2

公开(公告)日：2019-03-05

申请号：US15717028

申请日：2017-09-27

Applicant: QUALCOMM Incorporated

Inventor： Jihoon Jeong ,  Francois Ibrahim Atallah ,  Keith Alan Bowman ,  David Joseph Winston Hansquine ,  Hoan Huu Nguyen

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/413 ,  G11C15/04 ,  G11C5/14 ,  G11C29/00 ,  G11C7/12 ,  G11C8/08

Abstract: Write-assist circuits for memory bit cells (“bit cells”) employing a P-type Field-Effect transistor (PFET) write port(s) are disclosed. Related methods and systems are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type Field-Effect transistor (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide bit cells having PFET write ports, as opposed to NFET write ports, to reduce memory write times to the bit cells, and thus improve memory performance. To mitigate a write contention that could otherwise occur when writing data to bit cells, a write-assist circuit provided in the form of negative wordline boost circuit can be employed to strengthen a PFET access transistor in a memory bit cell having a PFET write port(s).

公开(公告)号：US10026456B2

公开(公告)日：2018-07-17

申请号：US14862579

申请日：2015-09-23

Applicant: QUALCOMM Incorporated

Inventor： Jihoon Jeong ,  Francois Ibrahim Atallah ,  Keith Alan Bowman ,  David Joseph Winston Hansquine ,  Hoan Huu Nguyen

IPC: G11C11/00 ,  G11C5/14 ,  G11C11/419 ,  G11C11/413 ,  G11C15/04 ,  G11C7/12 ,  G11C8/08

Abstract: Write-assist circuits for memory bit cells (“bit cells”) employing a P-type Field-Effect transistor (PFET) write port(s) are disclosed. Related methods and systems are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type Field-Effect transistor (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide bit cells having PFET write ports, as opposed to NFET write ports, to reduce memory write times to the bit cells, and thus improve memory performance. To mitigate a write contention that could otherwise occur when writing data to bit cells, a write-assist circuit provided in the form of positive bitline boost circuit can be employed to strengthen a PFET access transistor in a memory bit cell having a PFET write port(s).

公开(公告)号：US20180033465A1

公开(公告)日：2018-02-01

申请号：US15717028

申请日：2017-09-27

Applicant: QUALCOMM Incorporated

Inventor： Jihoon Jeong ,  Francois Ibrahim Atallah ,  Keith Alan Bowman ,  David Joseph Winston Hansquine ,  Hoan Huu Nguyen

IPC: G11C5/14 ,  G11C11/419 ,  G11C7/12 ,  G11C11/413 ,  G11C8/08 ,  G11C15/04

CPC classification number: G11C11/00 ,  G11C5/14 ,  G11C7/12 ,  G11C8/08 ,  G11C11/413 ,  G11C11/419 ,  G11C15/04 ,  G11C29/00

Abstract: Write-assist circuits for memory bit cells (“bit cells”) employing a P-type Field-Effect transistor (PFET) write port(s) are disclosed. Related methods and systems are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type Field-Effect transistor (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide bit cells having PFET write ports, as opposed to NFET write ports, to reduce memory write times to the bit cells, and thus improve memory performance. To mitigate a write contention that could otherwise occur when writing data to bit cells, a write-assist circuit provided in the form of negative wordline boost circuit can be employed to strengthen a PFET access transistor in a memory bit cell having a PFET write port(s).