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    Boost and LDO hybrid converter with dual-loop control
    2.
    发明授权
    Boost and LDO hybrid converter with dual-loop control 有权

    公开(公告)号：US10411599B1

    公开(公告)日：2019-09-10

    申请号：US15937947

    申请日：2018-03-28

    Applicant: QUALCOMM Incorporated

    Inventor： Chunlei Shi ,  Jongrit Lerdworatawee ,  Yu Pu

    IPC: H02M3/156 ,  H02M3/158 ,  G05F1/26 ,  H02M1/00 ,  G05F1/45

    Abstract: A boost and LDO hybrid converter with dual-loop control is disclosed. In some implementations, a hybrid converter includes an inductor having a first terminal to receive an input voltage and a second terminal; an n-type metal oxide semiconductor device (nMOS) having a drain coupled to the second terminal of the inductor; a p-type metal oxide semiconductor device (pMOS) having a gate, a drain, and a source, the source coupled to the second terminal of the inductor; an output capacitor having a first terminal coupled to the drain of the first pMOS; and a controller having a switch driver and a buffer, wherein the controller is configured to use the switch driver to drive the gate of the first pMOS in a boost mode and to use the buffer to drive the gate of the first pMOS in a low drop out (LDO) mode.

    Single-ended contention-free wide operating range level voltage shifter with built-in voltage boosting and down-stepping assisting circuitry
    3.
    发明授权
    Single-ended contention-free wide operating range level voltage shifter with built-in voltage boosting and down-stepping assisting circuitry 有权
    具有内置升压和下行辅助电路的单端无争用宽工作范围电平转换器

    公开(公告)号：US09515660B1

    公开(公告)日：2016-12-06

    申请号：US14843992

    申请日：2015-09-02

    Applicant: QUALCOMM Incorporated

    Inventor： Giby Samson ,  Yu Pu ,  Kendrick Hoy Leong Yuen

    IPC: H03K19/0185 ,  H03K17/687

    CPC classification number: H03K19/018507

    Abstract: A voltage level shifter to provide an output logic signal in response to an input logic signal, where the input logic signal is in a first voltage domain and the output logic signal is in a second voltage domain. In one embodiment, a voltage boost module provides a boosted voltage in response to the input logic signal going HIGH, where the boosted voltage is sufficient to turn OFF a pull-up transistor operating in the second voltage domain. Contention among pull-down and pull-up transistors may be avoided.

    Abstract translation: 电压电平移位器，用于响应于输入逻辑信号提供输出逻辑信号，其中输入逻辑信号处于第一电压域，并且输出逻辑信号处于第二电压域。 在一个实施例中，电压升压模块响应于输入逻辑信号变为高电平而提供升压电压，其中升压电压足以关闭在第二电压域中工作的上拉晶体管。 可以避免下拉和上拉晶体管之间的争用。

    CLOCK DISTRIBUTION SCHEMES WITH WIDE OPERATING VOLTAGE RANGES
    4.
    发明申请
    CLOCK DISTRIBUTION SCHEMES WITH WIDE OPERATING VOLTAGE RANGES 审中-公开
    具有宽操作电压范围的时钟分配方案

    公开(公告)号：US20160269009A1

    公开(公告)日：2016-09-15

    申请号：US14642859

    申请日：2015-03-10

    Applicant: QUALCOMM Incorporated

    Inventor： Giby Samson ,  Yu Pu ,  Kendrick Hoy Leong Yuen

    IPC: H03K5/135 ,  G06F1/10

    CPC classification number: H03K5/135 ,  G06F1/10 ,  H03K19/0016 ,  H03K2005/00052

    Abstract: Clock distribution schemes with wide operating voltage ranges are disclosed. In one aspect, an operating voltage level or condition within a computing device is sensed. In a first voltage condition, delay elements are used within a clock tree to minimize clock skew. In a second voltage condition, one or more delay and/or clocked elements are bypassed to minimize clock skew at the second voltage condition. In addition to controlling clock skew, power may be conserved by depowering the bypassed elements. Controlling clock skew in this fashion improves operation of a computing device that includes the clock tree and may improve battery life.

    Abstract translation: 公开了具有宽工作电压范围的时钟分配方案。 在一个方面，感测计算设备内的工作电压电平或状况。 在第一电压条件下，在时钟树中使用延迟元件以最小化时钟偏移。 在第二电压条件下，绕过一个或多个延迟和/或时钟元件以使在第二电压条件下的时钟偏移最小化。 除了控制时钟偏移之外，通过削弱旁路元件可以节省功率。 以这种方式控制时钟偏移改善了包括时钟树的计算设备的操作并且可以提高电池寿命。

    Apparatus and method for generating clock signal with low jitter and constant frequency while consuming low power
    8.
    发明授权
    Apparatus and method for generating clock signal with low jitter and constant frequency while consuming low power 有权

    公开(公告)号：US10581441B2

    公开(公告)日：2020-03-03

    申请号：US15706449

    申请日：2017-09-15

    Applicant: QUALCOMM Incorporated

    Inventor： Yu Pu ,  Jongrit Lerdworatawee ,  Chunlei Shi

    IPC: H03L7/06 ,  H03L7/187 ,  H03L7/07 ,  H03L7/197 ,  G01R31/317 ,  H03L7/099 ,  H02M3/335 ,  H03K3/0231

    Abstract: A clock signal generator includes ramp and threshold voltage generators. The clock signal generator further includes a comparator configured to initiate a first phase of a clock signal based on the ramp and threshold voltages applied to its first and second inputs, respectively. The comparator is further configured to initiate a second phase of the clock signal based on the ramp and threshold voltages applied to its second and first inputs, respectively. Because the application of the ramp and threshold voltages to the inputs of the comparator is swapped per phase of the clock signal, any offset voltage in the comparator does not affect the period of the clock signal because they cancel out after two-half periods. This ensures that the clock signal has a substantially constant frequency. Other features include enabling the high power consuming comparator during a small window to achieve low jitter and low average power consumption.

    APPARATUS AND METHOD FOR GENERATING CLOCK SIGNAL WITH LOW JITTER AND CONSTANT FREQUENCY WHILE CONSUMING LOW POWER
    9.
    发明申请
    APPARATUS AND METHOD FOR GENERATING CLOCK SIGNAL WITH LOW JITTER AND CONSTANT FREQUENCY WHILE CONSUMING LOW POWER 审中-公开

    公开(公告)号：US20190089364A1

    公开(公告)日：2019-03-21

    申请号：US15706449

    申请日：2017-09-15

    Applicant: QUALCOMM Incorporated

    Inventor： Yu Pu ,  Jongrit Lerdworatawee ,  Chunlei Shi

    IPC: H03L7/187 ,  H03L7/07 ,  H03L7/197 ,  H03L7/099 ,  H02M3/335 ,  G01R31/317

    Abstract: A clock signal generator includes ramp and threshold voltage generators. The clock signal generator further includes a comparator configured to initiate a first phase of a clock signal based on the ramp and threshold voltages applied to its first and second inputs, respectively. The comparator is further configured to initiate a second phase of the clock signal based on the ramp and threshold voltages applied to its second and first inputs, respectively. Because the application of the ramp and threshold voltages to the inputs of the comparator is swapped per phase of the clock signal, any offset voltage in the comparator does not affect the period of the clock signal because they cancel out after two-half periods. This ensures that the clock signal has a substantially constant frequency. Other features include enabling the high power consuming comparator during a small window to achieve low jitter and low average power consumption.

    Area and power efficient switchable supply network for powering multiple digital islands
    10.
    发明授权
    Area and power efficient switchable supply network for powering multiple digital islands 有权

    公开(公告)号：US09819189B2

    公开(公告)日：2017-11-14

    申请号：US14843983

    申请日：2015-09-02

    Applicant: QUALCOMM Incorporated

    Inventor： Chunlei Shi ,  Yu Pu ,  Kenneth David Easton ,  Kendrick Hoy Leong Yuen ,  Giby Samson

    IPC: G06F1/32 ,  H02J3/38 ,  H03K19/00

    CPC classification number: H02J3/38 ,  G06F1/3287 ,  H02J2003/388 ,  H03K19/0016

    Abstract: A switchable supply network for powering multiple digital islands. In one embodiment, a first digital island includes a first power collapsible circuit and a first retention circuit, and a second digital island includes a second power collapsible circuit and a second retention circuit. In a normal mode of operation, the first digital island is provided a first supply voltage and a second digital island is provided a second supply voltage higher than the first supply voltage. In a transition mode the second power collapsible circuit is powered down and the second supply voltage is lowered and provided to the second retention circuit. When the second supply voltage falls below the first supply voltage, the first power collapsible circuit is powered down. The second supply voltage is now provided only to the retention circuits, and is furthered lowered in a retention mode to a final retention voltage.

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