公开(公告)号：US20150050785A1

公开(公告)日：2015-02-19

申请号：US14496225

申请日：2014-09-25

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  Jun Yuan

IPC: H01L21/8238 ,  H01L21/84 ,  H01L21/28

CPC classification number: H01L21/823814 ,  H01L21/28026 ,  H01L21/823828 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/47 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

Abstract: A complementary metal-oxide-semiconductor (CMOS) device and methods of formation thereof are disclosed. In a particular example, a method of forming a CMOS device includes forming a first layer on an extension layer of a wafer, forming a first gate on a portion of the first layer, and forming an expansion region proximate to the extension layer. The method also includes removing a portion of the first gate to create a cavity and removing a portion of the first layer to extend the cavity to the extension layer.

Abstract translation: 公开了一种互补金属氧化物半导体（CMOS）器件及其形成方法。 在具体示例中，形成CMOS器件的方法包括在晶片的延伸层上形成第一层，在第一层的一部分上形成第一栅极，以及形成靠近延伸层的扩张区域。 该方法还包括去除第一栅极的一部分以产生空腔并去除第一层的一部分以将空腔延伸到延伸层。

公开(公告)号：US11387335B2

公开(公告)日：2022-07-12

申请号：US17061709

申请日：2020-10-02

Applicant: QUALCOMM Incorporated

Inventor： Junjing Bao ,  Jun Yuan ,  Peijie Feng

IPC: H01L29/417 ,  H01L29/40 ,  H01L29/423 ,  H01L21/768 ,  H01L21/3213 ,  H01L29/45

Abstract: Disclosed are optimized contract structures and fabrication techniques thereof. At least one aspect includes a semiconductor die. The semiconductor die includes a substrate and a contact disposed within the substrate. The contact includes a first portion with a first vertical cross-section having a first cross-sectional area. The first vertical cross-section has a first width and a first height. The contact also includes a second portion with a second vertical cross-section having a second cross-sectional area less than the first cross-sectional area. The second vertical cross-section includes a lower portion having the first width and a second height less than the first height, and an upper portion disposed above the lower portion and having a second width less than the first width and having a third height less than the first height.

公开(公告)号：US20210384310A1

公开(公告)日：2021-12-09

申请号：US16893993

申请日：2020-06-05

Applicant: QUALCOMM Incorporated

Inventor： Jun Yuan ,  Peijie Feng ,  Stanley Seungchul Song ,  Kern Rim

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L21/8234

Abstract: Gate-all-around (GAA) transistors with an additional bottom channel for reduced parasitic capacitance and methods of fabricating the same include one or more channels positioned between a source region and a drain region. The one or more channels, which may be nanowire or nanoslab semiconductors, are surrounded by gate material. The GAA transistor further includes an additional semiconductor channel between a bottom section of a gate material and a silicon on insulator (SOI) substrate in a GAA transistor. This additional channel, sometimes referred to as a bottom channel, may be thinner than other channels in the GAA transistor and may have a thickness less than its length.

公开(公告)号：US10181403B2

公开(公告)日：2019-01-15

申请号：US15910929

申请日：2018-03-02

Applicant: QUALCOMM Incorporated

Inventor： Da Yang ,  Yanxiang Liu ,  Jun Yuan ,  Kern Rim

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/66

Abstract: Multigate devices and fabrication methods that mitigate the layout effects are described. In conventional processes to fabricate multigate semiconductor devices such as FinFET devices, long isolation cut masks may be used. This can lead to undesirable layout effects. To mitigate or eliminate the layout effect, fabrication methods are proposed in which the interlayer dielectric (ILD) layer remains intact at the gate cut location during the fabrication process.

公开(公告)号：US10141305B2

公开(公告)日：2018-11-27

申请号：US15266214

申请日：2016-09-15

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Haining Yang ,  Jun Yuan ,  Kern Rim ,  Periannan Chidambaram

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L29/78

Abstract: Semiconductor devices employing Field Effect Transistors (FETs) with multiple channel structures without shallow trench isolation (STI) void-induced electrical shorts are disclosed. In one aspect, a semiconductor device is provided that includes a substrate. The semiconductor device includes channel structures disposed over the substrate, the channel structures corresponding to a FET. An STI trench is formed between each corresponding pair of channel structures. Each STI trench includes a bottom region filled with a lower quality oxide, and a top region filled with a higher quality oxide. The lower quality oxide is susceptible to void formation in the bottom region during particular fabrication steps of the semiconductor device. However, the higher quality oxide is not susceptible to void formation. Thus, the higher quality oxide does not include voids with which a gate may electrically couple to other active components, thus preventing STI void-induced electrical shorts in the semiconductor device.

公开(公告)号：US20160268256A1

公开(公告)日：2016-09-15

申请号：US14657021

申请日：2015-03-13

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  Jun Yuan

IPC: H01L27/088 ,  H01L29/161 ,  H01L21/02 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/16 ,  H01L29/165

CPC classification number: H01L27/088 ,  H01L21/823418 ,  H01L21/823487 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66356 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66666 ,  H01L29/7391 ,  H01L29/7827 ,  H01L29/7848 ,  H01L29/7851

Abstract: An apparatus includes a structure that includes a single substrate, a planar complementary metal-oxide semiconductor (CMOS) transistor formed on the single substrate, a planar tunnel field-effect transistor (TFET) formed on the single substrate, and a mobility enhancement strength layer included in the planar CMOS transistor or included in the planar TFET.

Abstract translation: 一种装置包括一种结构，其包括单个衬底，形成在单个衬底上的平面互补金属氧化物半导体（CMOS）晶体管，形成在单个衬底上的平面隧道场效应晶体管（TFET）和迁移率增强强度层 包括在平面CMOS晶体管中或包括在平面TFET中。