公开(公告)号：US20150179590A1

公开(公告)日：2015-06-25

申请号：US14251518

申请日：2014-04-11

Applicant: QUALCOMM Incorporated

Inventor： Jie Fu ,  Manuel Aldrete ,  Milind Pravin Shah

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L24/03 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/11 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/0903 ,  H01L2224/0912 ,  H01L2924/12042 ,  H01L2924/381 ,  H01L2924/00

Abstract: Some novel features pertain to an integrated device that includes a substrate, a first via, and a first bump pad. The first via traverses the substrate. The first via has a first via dimension. The first bump pad is on a surface of the substrate. The first bump pad is coupled to the first via. The first bump pad has a first pad dimension that is equal or less then the first via dimension. In some implementations, the integrated device includes a second via and a second bump pad. The second via traverses the substrate. The second via has a second via dimension. The second bump pad is on the surface of the substrate. The second bump pad is coupled to the second via. The second bump pad has a second pad dimension that is equal or less then the second via dimension.

Abstract translation: 一些新颖的特征涉及包括基板，第一通孔和第一凸块焊盘的集成装置。 第一个通孔穿过基板。 第一个通孔具有第一通孔尺寸。 第一凸块焊盘位于基板的表面上。 第一碰撞焊盘耦合到第一通孔。 第一凸块焊盘具有等于或小于第一通孔尺寸的第一焊盘尺寸。 在一些实施方案中，集成器件包括第二通孔和第二凸点焊盘。 第二个通孔穿过基板。 第二通孔具有第二通孔尺寸。 第二凸点焊盘位于基板的表面上。 第二凸点焊盘耦合到第二通孔。 第二凸块焊盘具有等于或小于第二通孔尺寸的第二焊盘尺寸。

公开(公告)号：US20140175658A1

公开(公告)日：2014-06-26

申请号：US13764959

申请日：2013-02-12

Applicant: QUALCOMM INCORPORATED

Inventor： Chin-Kwan Kim ,  Houssam W. Jomaa ,  Milind P. Shah ,  Manuel Aldrete ,  Omar J. Bchir

IPC: H01L21/50 ,  H01L23/48

CPC classification number: H01L23/48 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/13564 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81385 ,  H01L2924/07802 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: Sonic implementations pertain to a semiconductor device that includes a packaging substrate, a trace coupled to the packaging substrate, and a solder resist layer that covers part of the trace. The trace includes a first portion having a first width, and a second portion having a second width that is wider than the first width. In some implementations, the second portion having the second width increases the area of the trace coupled to the packaging substrate to reduce the likelihood of the trace peeling from the packaging substrate. In some implementations, the solder resist layer further includes an opening such that the second portion of the trace is exposed. In some implementations, the trace further includes a third portion located between the first portion and second portion of the trace and wherein the third portion of the trace is exposed through an opening in the solder resist layer.

Abstract translation: 声波实现涉及包括封装衬底，耦合到封装衬底的迹线和覆盖部分迹线的阻焊层的半导体器件。 迹线包括具有第一宽度的第一部分和具有宽于第一宽度的第二宽度的第二部分。 在一些实施方案中，具有第二宽度的第二部分增加了耦合到包装衬底的迹线的面积，以减少从包装衬底的迹线剥离的可能性。 在一些实施方案中，阻焊层还包括开口，使得迹线的第二部分被暴露。 在一些实施方案中，迹线还包括位于迹线的第一部分和第二部分之间的第三部分，并且其中迹线的第三部分通过阻焊层中的开口露出。