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    ANCHORING A TRACE ON A SUBSTRATE TO REDUCE PEELING OF THE TRACE
    2.
    发明申请
    ANCHORING A TRACE ON A SUBSTRATE TO REDUCE PEELING OF THE TRACE 审中-公开
    在基板上锚定一个跟踪以减少跟踪的剥离

    公开(公告)号：US20140175658A1

    公开(公告)日：2014-06-26

    申请号：US13764959

    申请日：2013-02-12

    Applicant: QUALCOMM INCORPORATED

    Inventor： Chin-Kwan Kim ,  Houssam W. Jomaa ,  Milind P. Shah ,  Manuel Aldrete ,  Omar J. Bchir

    IPC: H01L21/50 ,  H01L23/48

    CPC classification number: H01L23/48 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/13564 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81385 ,  H01L2924/07802 ,  H01L2924/00012 ,  H01L2924/00014

    Abstract: Sonic implementations pertain to a semiconductor device that includes a packaging substrate, a trace coupled to the packaging substrate, and a solder resist layer that covers part of the trace. The trace includes a first portion having a first width, and a second portion having a second width that is wider than the first width. In some implementations, the second portion having the second width increases the area of the trace coupled to the packaging substrate to reduce the likelihood of the trace peeling from the packaging substrate. In some implementations, the solder resist layer further includes an opening such that the second portion of the trace is exposed. In some implementations, the trace further includes a third portion located between the first portion and second portion of the trace and wherein the third portion of the trace is exposed through an opening in the solder resist layer.

    Abstract translation: 声波实现涉及包括封装衬底，耦合到封装衬底的迹线和覆盖部分迹线的阻焊层的半导体器件。 迹线包括具有第一宽度的第一部分和具有宽于第一宽度的第二宽度的第二部分。 在一些实施方案中，具有第二宽度的第二部分增加了耦合到包装衬底的迹线的面积，以减少从包装衬底的迹线剥离的可能性。 在一些实施方案中，阻焊层还包括开口，使得迹线的第二部分被暴露。 在一些实施方案中，迹线还包括位于迹线的第一部分和第二部分之间的第三部分，并且其中迹线的第三部分通过阻焊层中的开口露出。

    PACKAGE HAVING THERMAL COMPRESSION FLIP CHIP (TCFC) AND CHIP WITH REFLOW BONDING ON LEAD
    3.
    发明申请
    PACKAGE HAVING THERMAL COMPRESSION FLIP CHIP (TCFC) AND CHIP WITH REFLOW BONDING ON LEAD 审中-公开
    具有热压缩芯片（TCFC）和芯片的包装与引导连接

    公开(公告)号：US20140159238A1

    公开(公告)日：2014-06-12

    申请号：US13708221

    申请日：2012-12-07

    Applicant: QUALCOMM INCORPORATED

    Inventor： Manuel Aldrete ,  Milind P. Shah ,  Omar J. Bchir ,  Houssam W. Jomaa ,  Chin-Kwan Kim

    IPC: H01L23/488 ,  H01L23/00

    CPC classification number: H01L23/488 ,  H01L21/50 ,  H01L23/49838 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2924/014 ,  H01L2924/00014

    Abstract: Some exemplary implementations of this disclosure pertain to an integrated circuit package that includes a substrate, a first die and a second die. The substrate includes a first set of traces and a second set of traces. The first set of traces has a first pitch. The second set of traces has a second pitch. The first pitch is less than the second pitch. In some implementations, a pitch of a set of traces defines a center to center distance between two neighboring traces, or bonding pads on a substrate. The first die is coupled to the substrate by a thermal compression bonding process. In some implementations, the first die is coupled to the first set of traces of the substrate. The second die is coupled to the substrate by a reflow bonding process. In some implementations, the second die is coupled to the second set of traces of the substrate.

    Abstract translation: 本公开的一些示例性实施方式涉及包括基板，第一管芯和第二管芯的集成电路封装。 衬底包括第一组迹线和第二组迹线。 第一组轨迹具有第一音调。 第二组轨迹具有第二个间距。 第一节距小于第二节距。 在一些实施方案中，一组迹线的间距限定了两个相邻迹线之间的中心到中心距离，或者衬底上的接合焊盘。 第一管芯通过热压接工艺耦合到衬底。 在一些实施方式中，第一管芯耦合到衬底的第一组迹线。 第二管芯通过回流焊接工艺耦合到衬底。 在一些实施方式中，第二管芯耦合到衬底的第二组迹线。

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