公开(公告)号：US11258165B2

公开(公告)日：2022-02-22

申请号：US16236726

申请日：2018-12-31

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Chin-Kwan Kim ,  Jaehyun Yeon ,  Suhyung Hwang

IPC: H01Q1/38 ,  H01Q1/24 ,  H01Q9/12 ,  H01Q1/08 ,  H01Q5/364

Abstract: Certain aspects of the present disclosure provide an asymmetric antenna structure. An example antenna device generally includes a first antenna element, a second antenna element, and a flexible coupling element asymmetrically positioned between surfaces of the first and second antenna elements and electrically coupling the first antenna element to the second antenna element.

公开(公告)号：US09379090B1

公开(公告)日：2016-06-28

申请号：US14622346

申请日：2015-02-13

Applicant: QUALCOMM Incorporated

Inventor： Ahmer Raza Syed ,  Chin-Kwan Kim ,  Omar James Bchir ,  Milind Pravin Shah ,  Ryan David Lane

IPC: H01L23/34 ,  H01L25/065 ,  H01L23/538 ,  H01L23/367 ,  H01L23/00 ,  H01L21/683 ,  H01L25/00

CPC classification number: H01L25/0655 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/145 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5385 ,  H01L24/32 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68372 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/83191 ,  H01L2224/92225 ,  H01L2924/15158 ,  H01L2924/15333

Abstract: A semiconductor package for a side by side die configuration may include a substrate having a cavity, a bridge interposer positioned within the cavity and having an active side facing active sides of a first die and a second die and partially horizontally overlapping the first die and the second die to provide an interconnection between the first die and the second die, and a thermal element attached to backsides of the first die and the second die to provide a heat path and heat storage for the first die and the second die.

Abstract translation: 用于并排管芯构造的半导体封装可以包括具有空腔的衬底，位于空腔内的桥插入器，并且具有面向第一管芯和第二管芯的主动侧的有源侧，并且部分水平地与第一管芯重叠， 第二模具以提供第一模具和第二模具之间的互连，以及附接到第一模具和第二模具的背面的热元件，以为第一模具和第二模具提供热路径和热存储。

公开(公告)号：US20150116965A1

公开(公告)日：2015-04-30

申请号：US14067677

申请日：2013-10-30

Applicant: Qualcomm Incorporated

Inventor： Chin-Kwan Kim ,  Omar James Bchir ,  Dong Wook Kim ,  Hong Bok We

IPC: H05K1/18 ,  H05K1/11

CPC classification number: H05K1/18 ,  H01L23/5383 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/15192 ,  H01L2924/15313 ,  H05K1/11 ,  H01L2924/014

Abstract: Some novel features pertain to a substrate that includes a first dielectric layer and a bridge structure. The bridge structure is embedded in the first dielectric layer. The bridge structure is configured to provide an electrical connection between a first die and a second die. The first and second dies are configured to be coupled to the substrate. The bridge structure includes a first set of interconnects and a second dielectric layer. The first set of interconnects is embedded in the first dielectric layer. In some implementations, the bridge structure further includes a second set of interconnects. In some implementations, the second dielectric layer is embedded in the first dielectric layer. The some implementations, the first dielectric layer includes the first set of interconnects of the bridge structure, a second set of interconnects in the bridge structure, and a set of pads in the bridge structure.

Abstract translation: 一些新颖的特征涉及包括第一介电层和桥结构的基板。 桥结构嵌入在第一电介质层中。 桥结构构造成在第一管芯和第二管芯之间提供电连接。 第一和第二管芯被配置为耦合到衬底。 桥结构包括第一组互连和第二介电层。 第一组互连嵌入在第一介质层中。 在一些实现中，桥结构还包括第二组互连。 在一些实施方案中，第二介电层被嵌入在第一介电层中。 在一些实施方式中，第一介电层包括桥结构的第一组互连，桥结构中的第二组互连以及桥结构中的一组焊盘。

公开(公告)号：US20230307817A1

公开(公告)日：2023-09-28

申请号：US17651324

申请日：2022-02-16

Applicant: QUALCOMM Incorporated

Inventor： Suhyung Hwang ,  Kun Fang ,  Jaehyun Yeon ,  Chin-Kwan Kim ,  Taesik Yang

IPC: H01Q1/22 ,  H01Q9/04 ,  H01Q21/06

CPC classification number: H01Q1/2283 ,  H01Q9/045 ,  H01Q21/065

Abstract: Antenna modules employing a package substrate with a vertically-integrated patch antenna(s), and related fabrication methods. The antenna module includes a radiofrequency (RF) IC (RFIC) package that includes one or more RFICs for supporting RF communications and a package substrate that includes one or more metallization layers with formed metal interconnects for routing of signals between the RFICs and an antenna(s) in the package substrate. The package substrate includes one or more patch antennas that are planar-shaped and vertically integrated in a plurality of metallization layers in the package substrate, behaving electromagnetically as a patch antenna. In this manner, the patch antenna(s) can be formed as a vertically-integrated structure in the package substrate with fabrication methods used for fabricating metal interconnects and vias (e.g., a micro via fabrication process) in package substrates.

公开(公告)号：US10410971B2

公开(公告)日：2019-09-10

申请号：US15689967

申请日：2017-08-29

Applicant: QUALCOMM Incorporated

Inventor： David Fraser Rae ,  Hong Bok We ,  Christopher Healy ,  Chin-Kwan Kim

IPC: H01L23/13 ,  H01L23/552 ,  H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L21/3205 ,  H01L23/373 ,  H01L23/498 ,  H01L23/367

Abstract: A package that includes an integrated device partially enclosed in a conductive material and embedded in a package substrate. The package includes a package substrate having a first cavity, the integrated device having a first active side and an inactive side embedded in the first cavity, and a structure partially enclosing the integrated device having a first layer and a second layer, wherein the first layer is coupled between the package substrate and the integrated device, and wherein the second layer is disposed over the inactive side of the integrated device.

公开(公告)号：US10325855B2

公开(公告)日：2019-06-18

申请号：US15074750

申请日：2016-03-18

Applicant: QUALCOMM Incorporated

Inventor： Daeik Kim ,  Jie Fu ,  Changhan Yun ,  Chin-Kwan Kim ,  Manuel Aldrete ,  Chengjie Zuo ,  Mario Velez ,  Jonghae Kim

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/768 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00

Abstract: A device and method of fabricating are provided. The device includes a substrate having a first side and an opposite second side, a cavity defined within the substrate from the first side, a die coupled to a floor of the cavity and having a conductive pad on a side of the die distal to the floor of the cavity. A laminate layer coupled to the second side of the substrate may be included. A hole may be drilled, at one time, through layers of the device, through the die, and through the conductive pad. The hole extends through and is defined within the laminate layer (if present), the second side of the substrate, the die, and the conductive pad. A conductive material is provided within the hole and extends between and through the laminate layer (if provided), the second side of the substrate, the die, and the conductive pad.

公开(公告)号：US10163871B2

公开(公告)日：2018-12-25

申请号：US15097719

申请日：2016-04-13

Applicant: QUALCOMM Incorporated

Inventor： Rajneesh Kumar ,  Chin-Kwan Kim ,  Milind Shah

IPC: H01L25/10 ,  H01L23/552 ,  H01L23/66 ,  H01L25/065 ,  H04W4/80 ,  H01L25/00 ,  H04W4/00 ,  H01L23/00 ,  H01L25/16 ,  H01L21/56

Abstract: An integrated device that includes a printed circuit board (PCB) and a package on package (PoP) device coupled to the printed circuit board (PCB). The package on package (PoP) device includes a first package that includes a first electronic package component (e.g., first die) and a second package coupled to the first package. The integrated device includes a first encapsulation layer formed between the first package and the second package. The integrated device includes a second encapsulation layer that at least partially encapsulates the package on package (PoP) device. The integrated device is configured to provide cellular functionality, wireless fidelity functionality and Bluetooth functionality. In some implementations, the first encapsulation layer is separate from the second encapsulation layer. In some implementations, the second encapsulation layer includes the first encapsulation layer. The package on package (PoP) device includes a gap controller located between the first package and the second package.

公开(公告)号：US09947642B2

公开(公告)日：2018-04-17

申请号：US15069525

申请日：2016-03-14

Applicant: QUALCOMM Incorporated

Inventor： Rajneesh Kumar ,  Chin-Kwan Kim ,  Brian Roggeman

IPC: H01L25/10 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L25/105 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/01029

Abstract: A package on package (PoP) device that includes a first package, a second package that is coupled to the first package, and at least one gap controller located between the first package and the second package, where the at least one gap controller is configured to provide a minimum gap between the first package and the second package. The first package includes a first electronic package component (e.g., first die). In some implementations, the at least one gap controller is coupled to the first package, but free of coupling with the second package. The at least one gap controller is located on or about a center of the first package. The at least one gap controller may be located between the first electronic package component (e.g., first die) and the second package. The package on package (PoP) device may include an encapsulation layer between the first package and the second package.

公开(公告)号：US09806063B2

公开(公告)日：2017-10-31

申请号：US14699863

申请日：2015-04-29

Applicant: QUALCOMM Incorporated

Inventor： Chin-Kwan Kim ,  Rajneesh Kumar ,  Vladimir Noveski ,  Jie Fu ,  Ahmer Raza Syed ,  Milind Pravin Shah ,  Omar James Bchir

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/16 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L21/56 ,  H01L23/538

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/568 ,  H01L21/768 ,  H01L23/16 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Some features pertain to a package that includes a redistribution portion, a first die coupled to the redistribution portion, a core layer coupled to the redistribution portion, and an encapsulation layer encapsulating the first die and the core layer. The redistribution portion includes a first dielectric layer. The core layer has a higher Young's Modulus than the encapsulation layer. In some implementations, the core layer includes a glass fiber (e.g., core layer is a glass reinforced dielectric layer). In some implementations, the core layer has a Young's Modulus of about at least 15 gigapascals (Gpa). In some implementations, the first die includes a front side and a back side, where the front side of the first die is coupled to the redistribution portion. In some implementations, the first dielectric layer is a photo imageable dielectric (PID) layer.

公开(公告)号：US09609751B2

公开(公告)日：2017-03-28

申请号：US14251486

申请日：2014-04-11

Applicant: QUALCOMM Incorporated

Inventor： Houssam Wafic Jomaa ,  Omar James Bchir ,  Chin-Kwan Kim

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/42 ,  H01L23/498

CPC classification number: H05K1/112 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/0298 ,  H05K3/422 ,  H05K3/425 ,  H05K3/429 ,  H05K2201/0344 ,  H05K2201/09036 ,  H05K2201/10378

Abstract: Some novel features pertain to a substrate that includes a first dielectric layer, a first interconnect, a first cavity, and a first electroless metal layer. The first dielectric layer includes a first surface and a second surface. The first interconnect is on the first surface of the substrate layer. The first cavity traverses the first surface of the first dielectric layer. The first electroless metal layer is formed at least partially in the first cavity. The first electroless metal layer defines a second interconnect embedded in the first dielectric layer. In some implementations, the substrate further includes a core layer. The core layer includes a first surface and a second surface. The first surface of the core layer is coupled to the second surface of the first dielectric layer. In some implementations, the substrate further includes a second dielectric layer.