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    ANCHORING A TRACE ON A SUBSTRATE TO REDUCE PEELING OF THE TRACE
    2.
    发明申请
    ANCHORING A TRACE ON A SUBSTRATE TO REDUCE PEELING OF THE TRACE 审中-公开
    在基板上锚定一个跟踪以减少跟踪的剥离

    公开(公告)号：US20140175658A1

    公开(公告)日：2014-06-26

    申请号：US13764959

    申请日：2013-02-12

    Applicant: QUALCOMM INCORPORATED

    Inventor： Chin-Kwan Kim ,  Houssam W. Jomaa ,  Milind P. Shah ,  Manuel Aldrete ,  Omar J. Bchir

    IPC: H01L21/50 ,  H01L23/48

    CPC classification number: H01L23/48 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/13564 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81385 ,  H01L2924/07802 ,  H01L2924/00012 ,  H01L2924/00014

    Abstract: Sonic implementations pertain to a semiconductor device that includes a packaging substrate, a trace coupled to the packaging substrate, and a solder resist layer that covers part of the trace. The trace includes a first portion having a first width, and a second portion having a second width that is wider than the first width. In some implementations, the second portion having the second width increases the area of the trace coupled to the packaging substrate to reduce the likelihood of the trace peeling from the packaging substrate. In some implementations, the solder resist layer further includes an opening such that the second portion of the trace is exposed. In some implementations, the trace further includes a third portion located between the first portion and second portion of the trace and wherein the third portion of the trace is exposed through an opening in the solder resist layer.

    Abstract translation: 声波实现涉及包括封装衬底，耦合到封装衬底的迹线和覆盖部分迹线的阻焊层的半导体器件。 迹线包括具有第一宽度的第一部分和具有宽于第一宽度的第二宽度的第二部分。 在一些实施方案中，具有第二宽度的第二部分增加了耦合到包装衬底的迹线的面积，以减少从包装衬底的迹线剥离的可能性。 在一些实施方案中，阻焊层还包括开口，使得迹线的第二部分被暴露。 在一些实施方案中，迹线还包括位于迹线的第一部分和第二部分之间的第三部分，并且其中迹线的第三部分通过阻焊层中的开口露出。

    PACKAGE HAVING THERMAL COMPRESSION FLIP CHIP (TCFC) AND CHIP WITH REFLOW BONDING ON LEAD
    4.
    发明申请
    PACKAGE HAVING THERMAL COMPRESSION FLIP CHIP (TCFC) AND CHIP WITH REFLOW BONDING ON LEAD 审中-公开
    具有热压缩芯片（TCFC）和芯片的包装与引导连接

    公开(公告)号：US20140159238A1

    公开(公告)日：2014-06-12

    申请号：US13708221

    申请日：2012-12-07

    Applicant: QUALCOMM INCORPORATED

    Inventor： Manuel Aldrete ,  Milind P. Shah ,  Omar J. Bchir ,  Houssam W. Jomaa ,  Chin-Kwan Kim

    IPC: H01L23/488 ,  H01L23/00

    CPC classification number: H01L23/488 ,  H01L21/50 ,  H01L23/49838 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2924/014 ,  H01L2924/00014

    Abstract: Some exemplary implementations of this disclosure pertain to an integrated circuit package that includes a substrate, a first die and a second die. The substrate includes a first set of traces and a second set of traces. The first set of traces has a first pitch. The second set of traces has a second pitch. The first pitch is less than the second pitch. In some implementations, a pitch of a set of traces defines a center to center distance between two neighboring traces, or bonding pads on a substrate. The first die is coupled to the substrate by a thermal compression bonding process. In some implementations, the first die is coupled to the first set of traces of the substrate. The second die is coupled to the substrate by a reflow bonding process. In some implementations, the second die is coupled to the second set of traces of the substrate.

    Abstract translation: 本公开的一些示例性实施方式涉及包括基板，第一管芯和第二管芯的集成电路封装。 衬底包括第一组迹线和第二组迹线。 第一组轨迹具有第一音调。 第二组轨迹具有第二个间距。 第一节距小于第二节距。 在一些实施方案中，一组迹线的间距限定了两个相邻迹线之间的中心到中心距离，或者衬底上的接合焊盘。 第一管芯通过热压接工艺耦合到衬底。 在一些实施方式中，第一管芯耦合到衬底的第一组迹线。 第二管芯通过回流焊接工艺耦合到衬底。 在一些实施方式中，第二管芯耦合到衬底的第二组迹线。

    PACKAGE SUBSTRATE WITH TESTING PADS ON FINE PITCH TRACES
    6.
    发明申请
    PACKAGE SUBSTRATE WITH TESTING PADS ON FINE PITCH TRACES 有权
    包装衬底，带有测试垫

    公开(公告)号：US20140247573A1

    公开(公告)日：2014-09-04

    申请号：US13783168

    申请日：2013-03-01

    Applicant: QUALCOMM INCORPORATED

    Inventor： Chin-Kwan Kim ,  Kuiwon Kang ,  Omar J. Bchir

    IPC: H05K1/11 ,  H05K3/22 ,  H05K3/30

    CPC classification number: H05K1/111 ,  G01R31/2818 ,  H05K1/0268 ,  H05K3/3452 ,  H05K2201/10674 ,  Y10T29/49004 ,  Y10T29/49124 ,  Y10T29/4913

    Abstract: Some implementations provide a substrate that includes several traces, a solder resist layer covering the several traces, and a testing pad coupled to a trace from the several traces. The testing pad is at least partially exposed and at least partially free of the solder resist layer when a chip is coupled to the substrate. In some implementations, the several traces have a pitch that is 100 microns (nm) or less. In some implementations, the substrate is a package substrate. In some implementations, the package substrate is a package substrate on which a thermal compression flip chip is mounted during an assembly process. In some implementations, the testing pad is free of a direct connection with a bonding component of the chip when the chip is coupled to the substrate. In some implementations, the bonding component is one of a solder ball.

    Abstract translation: 一些实施方案提供了包括几条迹线的衬底，覆盖几条迹线的阻焊层，以及耦合到几条迹线的迹线的测试焊盘。 当芯片耦合到衬底时，测试焊盘至少部分地暴露并且至少部分地不含阻焊层。 在一些实施方案中，几条迹线具有100微米（nm）或更小的间距。 在一些实施方式中，衬底是封装衬底。 在一些实施方案中，封装衬底是在组装过程期间安装热压缩倒装芯片的封装衬底。 在一些实施方案中，当芯片耦合到衬底时，测试焊盘不与芯片的焊接部件直接连接。 在一些实施方式中，接合部件是焊球之一。

    SUBSTRATE HAVING A LOW COEFFICIENT OF THERMAL EXPANSION (CTE) COPPER COMPOSITE MATERIAL
    8.
    发明申请
    SUBSTRATE HAVING A LOW COEFFICIENT OF THERMAL EXPANSION (CTE) COPPER COMPOSITE MATERIAL 审中-公开
    具有低膨胀系数（CTE）铜复合材料的衬底

    公开(公告)号：US20140138129A1

    公开(公告)日：2014-05-22

    申请号：US13715235

    申请日：2012-12-14

    Applicant: QUALCOMM INCORPORATED

    Inventor： Layal L. Rouhana ,  Jomaa Houssam W. ,  Omar J. Bchir

    IPC: H05K3/10 ,  H05K1/09

    CPC classification number: H05K1/092 ,  B82Y30/00 ,  H05K1/09 ,  H05K3/108 ,  H05K3/1258 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4664 ,  H05K2201/026 ,  H05K2201/0323 ,  H05K2201/0329 ,  H05K2201/068 ,  H05K2201/09563 ,  H05K2203/0723

    Abstract: Some implementations provide a substrate that includes a first dielectric layer, a second dielectric layer, a core layer, and a composite conductive trace. The first and second dielectric layers have a first coefficient of thermal expansion (CTE). The core layer is between the first dielectric layer and the second dielectric layer. The composite conductive trace is between the first dielectric layer and the second dielectric layer. The composite conductive trace includes copper and another material. The composite conductive trace has a second CTE that is less than a third CTE for copper to more closely match the first CTE for the first and second dielectric layers.

    Abstract translation: 一些实施方案提供了包括第一介电层，第二介电层，芯层和复合导电迹线的基板。 第一和第二介电层具有第一热膨胀系数（CTE）。 芯层在第一介电层和第二介电层之间。 复合导电迹线在第一介电层和第二介电层之间。 复合导电迹线包括铜和另一种材料。 复合导电迹线具有小于第三CTE的第二CTE，铜对于第一和第二电介质层更紧密地匹配第一CTE。

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