公开(公告)号：US20180196681A1

公开(公告)日：2018-07-12

申请号：US15402631

申请日：2017-01-10

Applicant: QUALCOMM Incorporated

Inventor： Lior Amarilio ,  Sharon Graif ,  Oren Nishry

IPC: G06F9/44 ,  G06F13/364 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F13/404 ,  G06F13/364 ,  G06F13/4282 ,  Y02D10/14 ,  Y02D10/151

Abstract: Selective processor wake-up in an electronic device is provided. In one aspect, a master circuit in an electronic device is communicatively coupled to a data bus that includes a primary data line and a plurality of secondary data lines preconfigured to identify a plurality of processors in the electronic device, respectively. The master circuit detects a processor wake-up trigger(s) asserted on a secondary data line(s) and wakes up a target processor(s) identified by the secondary data line(s). In another aspect, a client circuit(s) identifies the secondary data line(s) preconfigured to identify the target processor(s) and asserts the processor wake-up trigger(s) on the secondary data line(s). By conveying the processor wake-up trigger(s) over the secondary data line(s) preconfigured to identify the target processor(s), it may be possible to optimize processor wake-up efficiency and responsiveness in the master circuit, thus leading to improved power consumption and battery life in the electronic device.

公开(公告)号：US12164460B2

公开(公告)日：2024-12-10

申请号：US17923110

申请日：2021-04-16

Applicant: QUALCOMM Incorporated

Inventor： Sharon Graif ,  Navdeep Mer ,  Naveen Kumar Narala ,  Sriharsha Chakka

IPC: G06F13/42 ,  G06F13/40

Abstract: Systems, methods, and apparatus are configured to enable a receiver to provide feedback. In one example, a method performed at a device coupled to a serial bus includes receiving a write command from the serial bus in a datagram, writing a data byte received in a first data frame of the datagram to a register address identified by the datagram, and using a second data frame of the datagram to provide feedback regarding the datagram. Feedback may be provided by driving a data line of the serial bus to provide a negative acknowledgement during the second data frame when a transmission error is detected in the datagram, and refraining from driving the data line of the serial bus during the second data frame when no transmission error is detected in the datagram, thereby providing an acknowledgement of the datagram.

公开(公告)号：US11522738B1

公开(公告)日：2022-12-06

申请号：US17354332

申请日：2021-06-22

Applicant: QUALCOMM Incorporated

Inventor： Tomer Rafael Ben-Chen ,  Sharon Graif ,  Lior Amarilio

IPC: H04L25/49 ,  H04W72/04 ,  H04L25/03 ,  H03K19/21 ,  H04B1/40

Abstract: High-speed communication links with self-aligned scrambling on a communication link that sends scrambled signals may include a slave device that may self-align by initially detecting an unscrambled preamble symbol and more particularly detect an edge of the unscrambled preamble symbol. Based on the detected edge, a fine alignment adjustment may be made by testing subsequent scrambled data for a repeated pattern such as an IDLE symbol by comparing the repeated pattern to a candidate scrambled sequence that has been received through the communication link. The comparison may use an exclusive OR (XOR) circuit on some bits to derive a scrambler seed that is used to test for a match for the remaining bits. If there is a match, the scrambler seed and frame alignment have been detected and alignment is achieved.

公开(公告)号：US11360916B2

公开(公告)日：2022-06-14

申请号：US17005143

申请日：2020-08-27

Applicant: QUALCOMM Incorporated

Inventor： Sharon Graif ,  Navdeep Mer ,  Lior Amarilio

IPC: G06F13/16 ,  G06F1/28 ,  G06F13/42 ,  G06F13/40 ,  G06F11/07

Abstract: Systems, methods, and apparatus are configured to enable a receiver to provide feedback. A feedback mechanism enables a transmitting device to identify the provider of feedback for a multicast transmission, and the feedback transmitted by one or more individual receivers of the multicast transmission. A method includes receiving a multicast write command from the serial bus in a first datagram, writing a data byte received in a first data frame of the first datagram to a register address identified by the first datagram, and providing device-specific feedback regarding the first datagram in a multibit slot within the second data frame. The multibit slot is one of a plurality of sequential multibit slots defined for the second data frame. Each multibit slot in the plurality of sequential multibit slots may provide device-specific feedback from one receiving device addressed by the multicast write command.

公开(公告)号：US11354266B2

公开(公告)日：2022-06-07

申请号：US16997542

申请日：2020-08-19

Applicant: QUALCOMM Incorporated

Inventor： Sharon Graif ,  Kishalay Haldar ,  Navdeep Mer ,  Viney Kumar ,  Sriharsha Chakka

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/374

Abstract: The systems and methods for hang correction in a power management interface bus cause secondary master devices associated with the power management interface bus to utilize timers to determine if a master that won arbitration has asserted a clock signal within a predefined amount of time. If a timer for a secondary master device expires without a clock signal being asserted by the winning master, the secondary master will assume ownership of the bus and assert a clock signal. Priorities between secondary masters are created by using a master identification (MID) value assigned during bus enumeration to determine a timer value. By allowing the secondary masters to assume ownership after expiration of respective timers, bus ownership is maintained in the event that a winning master hangs and does not assert ownership.

公开(公告)号：US20220058154A1

公开(公告)日：2022-02-24

申请号：US16997542

申请日：2020-08-19

Applicant: QUALCOMM Incorporated

Inventor： Sharon Graif ,  Kishalay Haldar ,  Navdeep Mer ,  Viney Kumar ,  Sriharsha Chakka

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/374

Abstract: The systems and methods for hang correction in a power management interface bus cause secondary master devices associated with the power management interface bus to utilize timers to determine if a master that won arbitration has asserted a clock signal within a predefined amount of time. If a timer for a secondary master device expires without a clock signal being asserted by the winning master, the secondary master will assume ownership of the bus and assert a clock signal. Priorities between secondary masters are created by using a master identification (MID) value assigned during bus enumeration to determine a timer value. By allowing the secondary masters to assume ownership after expiration of respective timers, bus ownership is maintained in the event that a winning master hangs and does not assert ownership.

公开(公告)号：US11064295B2

公开(公告)日：2021-07-13

申请号：US16597902

申请日：2019-10-10

Applicant: QUALCOMM Incorporated

Inventor： Lior Amarilio ,  Yiftach Benjamini ,  Sharon Graif

IPC: H04R3/00 ,  G06F3/16 ,  H04R3/04 ,  G10L21/0208 ,  H04L29/06 ,  G06F9/30

Abstract: Systems and methods for scrambling data-port audio in SOUNDWIRE™ systems include a scramble enable feature that allows a data source to scramble an outgoing channel content with a cyclic linear feedback shift register (LFSR) using a pseudo-random binary sequence (PRBS) such as, but not limited to, the PRBS defined in the SOUNDWIRE specification. Data ports for audio sinks receiving the scrambled content descramble the content for use by the audio sink. In a specific exemplary aspect, an output of the LFSR is added or subtracted with the audio data to make the microphones independent of one another and reduce crosstalk.

公开(公告)号：US11010327B2

公开(公告)日：2021-05-18

申请号：US16519531

申请日：2019-07-23

Applicant: QUALCOMM Incorporated

Inventor： Sharon Graif ,  Meital Zangvil ,  Lior Amarilio

IPC: G06F13/42 ,  G06F13/24

Abstract: Systems, methods, and apparatus are described. A method for data communication performed at a master device includes configuring a serial interface for a point-to-point mode of operation, transmitting a first two-bit command through the serial interface, the two-bit command including a one-bit address and a read/write bit, and initiating a transaction through the serial interface. The transaction may be identified by the two-bit command and is conducted in accordance with an I3C protocol. The transaction may include the transfer of one or more data frames formatted in accordance with the I3C protocol. The method may include receiving an acknowledgement from a slave device in response to the first two-bit command.

公开(公告)号：US10713199B2

公开(公告)日：2020-07-14

申请号：US16012532

申请日：2018-06-19

Applicant: QUALCOMM Incorporated

Inventor： Lior Amarilio ,  Amit Gil ,  Sharon Graif

IPC: G06F13/364 ,  G06F1/08 ,  G06F3/16 ,  H04R3/00 ,  H04R3/12 ,  G06F13/42 ,  G06F1/12

Abstract: System, methods and apparatus are described that can improve available bandwidth on a SoundWire bus without increasing the number of pins used by the SoundWire bus. A method performed at a master device coupled to a SoundWire bus includes providing a clock signal by a first master device over a clock line of a SoundWire bus to a first slave device and a second slave device coupled to the SoundWire bus, transmitting first control information from the first master device to the first slave device over a first data line of the SoundWire bus, and transmitting second control information from the first master device to the second slave device over a second data line of the SoundWire bus. The first control information may be different from the second control information and is transmitted concurrently with the second control information.

公开(公告)号：US10572439B1

公开(公告)日：2020-02-25

申请号：US16447801

申请日：2019-06-20

Applicant: QUALCOMM Incorporated

Inventor： Sharon Graif ,  Meital Zangvil ,  Lior Amarilio

IPC: G06F13/42 ,  G06F13/40

Abstract: Systems, methods, and apparatus are described. An apparatus provides a clock signal, transmits an address on a second line of the serial bus followed by a read/write bit configured to initiate a read transaction, and delays a pulse in the clock signal after transmitting the read/write bit. The pulse may be delayed for a first duration configured to accommodate a latency associated with a first slave device that is a participant in the read transaction. The apparatus may receive an acknowledgement from the first slave device while the pulse is being transmitted and may receive a first data byte from the first slave device after receiving the acknowledgment. The apparatus may stall the clock signal for a second duration after receiving the first data byte from the first slave device, and receive a second data byte from the first slave device after the acknowledgment.