公开(公告)号：US06660578B1

公开(公告)日：2003-12-09

申请号：US10118274

申请日：2002-04-08

Applicant: Olov Karlsson ,  Qi Xiang ,  HaiHong Wang ,  Bin Yu ,  Zoran Krivokapic

Inventor： Olov Karlsson ,  Qi Xiang ,  HaiHong Wang ,  Bin Yu ,  Zoran Krivokapic

IPC: H01L218238

CPC classification number: H01L27/1203 ,  H01L21/84

Abstract: A semiconductor device, a semiconductor wafer and a method of forming a semiconductor wafer where a barrier layer is used to inhibit P-type ion-penetration into a dielectric layer made from a high-K material.

Abstract translation: 半导体器件，半导体晶片和形成半导体晶片的方法，其中阻挡层用于抑制由高K材料制成的电介质层中的P型离子渗透。

公开(公告)号：US06630720B1

公开(公告)日：2003-10-07

申请号：US10036210

申请日：2001-12-26

Applicant: Witold P. Maszara ,  HaiHong Wang ,  Qi Xiang

Inventor： Witold P. Maszara ,  HaiHong Wang ,  Qi Xiang

IPC: H01L2976

CPC classification number: H01L21/823842 ,  H01L21/0337 ,  H01L21/84 ,  H01L27/1203

Abstract: An asymmetric semiconductor device and a method of making a pair of the asymmetric devices. The semiconductor device includes a layer of semiconductor material having a source and a drain, and a dual work function gate disposed on the layer of semiconductor material to define a channel interposed between the source and the drain.

Abstract translation: 非对称半导体器件和制造一对不对称器件的方法。 半导体器件包括具有源极和漏极的半导体材料层，以及设置在半导体材料层上以限定插入在源极和漏极之间的沟道的双功函数栅极。

公开(公告)号：US06602781B1

公开(公告)日：2003-08-05

申请号：US09734207

申请日：2000-12-12

Applicant: Qi Xiang ,  Paul R. Besser ,  Matthew Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

Inventor： Qi Xiang ,  Paul R. Besser ,  Matthew Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

IPC: H01L2144

CPC classification number: H01L21/28202 ,  H01L21/28097 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/7833

Abstract: A method for implementing a self-aligned metal silicide gate is achieved by confining a metal within a recess overlying a channel and annealing to cause metal and its overlying silicon to interact to form the self-aligned metal silicide gate. A gate dielectric layer formed of oxynitride or a nitride/oxide stack is formed on the bottom and sidewalls of the recess prior to depositing the silicon. The metal is removed except for the portion of the metal in the recess. A planarization step is performed to remove the remaining unreacted silicon by chemical mechanical polishing until no silicon is detected.

Abstract translation: 实现自对准金属硅化物栅极的方法是通过将金属限制在覆盖沟道的凹槽内并退火以使金属及其上覆的硅相互作用以形成自对准的金属硅化物栅极来实现的。 在沉积硅之前，在凹陷的底部和侧壁上形成由氧氮化物或氮化物/氧化物堆叠形成的栅极电介质层。 除了金属在凹部中的部分之外，除去金属。 进行平面化步骤以通过化学机械抛光除去剩余的未反应的硅，直到没有检测到硅。

公开(公告)号：US06524929B1

公开(公告)日：2003-02-25

申请号：US09794894

申请日：2001-02-26

Applicant: Qi Xiang ,  Philip A. Fisher

Inventor： Qi Xiang ,  Philip A. Fisher

IPC: H01L2176

CPC classification number: H01L21/76264 ,  H01L21/76283

Abstract: A method of isolation of active islands on a silicon-on-insulator semiconductor device, comprising the steps of providing a silicon-on-insulator semiconductor wafer having a silicon active layer, a dielectric insulation layer and a silicon substrate; forming an isolation trench through the silicon active layer, the isolation trench defining at least one active island in the silicon active layer; depositing a passivating insulator in a lower portion of the isolation trench; and filling the isolation trench above the passivating insulator with a trench isolation material.

Abstract translation: 一种隔离绝缘体上半导体器件上的有源岛的方法，包括以下步骤：提供具有硅有源层，介电绝缘层和硅衬底的绝缘体上硅半导体晶片; 通过所述硅有源层形成隔离沟槽，所述隔离沟槽限定所述硅有源层中的至少一个有源岛; 在隔离沟槽的下部沉积钝化绝缘体; 以及用沟槽隔离材料填充钝化绝缘体上方的隔离沟槽。

公开(公告)号：US06465309B1

公开(公告)日：2002-10-15

申请号：US09734185

申请日：2000-12-12

Applicant: Qi Xiang ,  Paul R. Besser ,  Matthew Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

Inventor： Qi Xiang ,  Paul R. Besser ,  Matthew Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

IPC: H01L21336

CPC classification number: H01L21/28202 ,  H01L21/28097 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545

Abstract: A semiconductor structure and method for making the same provides a gate dielectric formed of oxynitride or a nitride/oxide stack formed within a recess. Amorphous silicon is deposited on the gate dielectric within the recess and a metal is deposited on the amorphous silicon. An annealing process forms a metal silicide gate within the recess on the gate dielectric. A wider range of metal materials can be selected because the gate dielectric formed of oxynitride or a nitride/oxide stack remains stable during the silicidation process. The metal silicide gate significantly reduces the sheet resistance between the gate and gate terminal.

Abstract translation: 半导体结构及其制造方法提供由氧氮化物形成的栅极电介质或形成在凹部内的氮化物/氧化物堆叠。 非晶硅沉积在凹槽内的栅极电介质上，金属沉积在非晶硅上。 退火工艺在栅极电介质的凹槽内形成金属硅化物栅极。 可以选择更宽范围的金属材料，因为由氮氧化物或氮化物/氧化物堆叠形成的栅极电介质在硅化过程中保持稳定。 金属硅化物栅极显着降低了栅极和栅极端子之间的薄层电阻。

公开(公告)号：US06440868B1

公开(公告)日：2002-08-27

申请号：US09691259

申请日：2000-10-19

Applicant: Paul R. Besser ,  Qi Xiang ,  Matthew S. Buynoski

Inventor： Paul R. Besser ,  Qi Xiang ,  Matthew S. Buynoski

IPC: H01L21302

CPC classification number: H01L21/28052 ,  H01L29/517 ,  H01L29/66545 ,  Y10S438/926

Abstract: A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a chemical vapor deposited layer of amorphous silicon on the high k gate dielectric. The metal is then deposited on the CVD amorphous silicon layer. An annealing process forms silicide in the gate, with a layer of silicon remaining unreacted. The work function of the metal gate is substantially the same as a polysilicon gate due to the presence of the CVD amorphous silicon layer.

Abstract translation: 半导体结构及其制造方法在硅衬底上提供金属栅极。 该栅极包括在该基板上的高介电常数和在该高k栅极电介质上的非晶硅化学气相沉积层。 然后将金属沉积在CVD非晶硅层上。 退火工艺在栅极中形成硅化物，其中一层硅残留未反应。 由于CVD非晶硅层的存在，金属栅极的功函数与多晶硅栅极基本相同。

公开(公告)号：US06376343B1

公开(公告)日：2002-04-23

申请号：US09812695

申请日：2001-03-21

Applicant: Matthew S. Buynoski ,  Paul R. Besser ,  Qi Xiang

Inventor： Matthew S. Buynoski ,  Paul R. Besser ,  Qi Xiang

IPC: H01L21425

CPC classification number: H01L29/6659 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/823814 ,  H01L29/665

Abstract: Deleterious roughness of metal silicide/doped Si interfaces arising during conventional salicide processing for forming shallow-depth source and drain junction regions of MOS transistors and/or CMOS devices due to poor compatibility of particular dopants and metal suicides is avoided, or at least substantially reduced, by implanting a first (main) dopant species having relatively good compatibility with the metal silicide, such that the maximum concentration thereof is at a depth above the depth to which silicidation reaction occurs and implanting a second (auxiliary) dopant species having relatively poor compatibility with the metal silicide, wherein the maximum concentration thereof is less than that of the first (main) dopant and is at a depth below the depth to which silicidation reaction occurs. The invention enjoys particular utility in forming NiSi layers on As-doped Si substrates.

Abstract translation: 避免了由于特定掺杂剂和金属硅化物的不良相容性而形成浅晶体管和/或CMOS器件的浅深度源极和漏极结区域的常规自对准硅化物处理期间产生的金属硅化物/掺杂Si界面的有缺陷的粗糙度，或至少大大降低 通过植入与金属硅化物具有相对良好的相容性的第一（主要）掺杂剂物质，使得其最大浓度在高于发生硅化反应的深度的深度处，并且注入具有相对较差相容性的第二（辅助）掺杂剂种类 金属硅化物，其中其最大浓度小于第一（主要）掺杂剂的最大浓度，并且处于低于发生硅化反应的深度的深度。 本发明特别适用于在掺杂Si的衬底上形成NiSi层。

公开(公告)号：US06291278B1

公开(公告)日：2001-09-18

申请号：US09303694

申请日：1999-05-03

Applicant: Qi Xiang ,  Matthew S. Buynoski ,  Ming-Ren Lin

Inventor： Qi Xiang ,  Matthew S. Buynoski ,  Ming-Ren Lin

IPC: H01L21336

CPC classification number: H01L21/76897 ,  H01L21/28518 ,  H01L21/823871 ,  H01L29/66545

Abstract: A method of fabricating a transistor having shallow source and drain extensions utilizes a self-aligned contact. The drain extensions are provided through an opening between a contact area and the gate structure. A high-K gate dielectric material can be utilized. P-MOS and N-MOS transistors can be created according to the disclosed method.

Abstract translation: 制造具有浅源极和漏极延伸的晶体管的方法利用自对准接触。 漏极延伸部分通过接触区域和栅极结构之间的开口提供。 可以使用高K栅介电材料。 可以根据所公开的方法创建P-MOS和N-MOS晶体管。

公开(公告)号：US06287918B1

公开(公告)日：2001-09-11

申请号：US09290086

申请日：1999-04-12

Applicant: Qi Xiang ,  Scott Allan Bell ,  Chih-Yuh Yang

Inventor： Qi Xiang ,  Scott Allan Bell ,  Chih-Yuh Yang

IPC: H01L21336

CPC classification number: H01L21/28079 ,  H01L21/28123 ,  H01L21/31683

Abstract: A process for fabricating a semiconductor device includes the formation of a metal device feature layer using lithographic techniques, followed by an oxidation process to reduce the lateral dimension of the metal device feature. The oxidation process is carried out by selectively, laterally oxidizing the metal composition of the device feature that overlies a dielectric layer. The lateral oxidation process forms metal oxide sidewall spacers on the device feature. Upon completion of the oxidation process, the metal oxide sidewall spacers are removed and a residual layer of unoxidized metal remains. The lateral dimension of the residual layer can be substantially less than that achievable by optical lithographic techniques.

Abstract translation: 制造半导体器件的方法包括使用光刻技术形成金属器件特征层，随后进行氧化处理以减小金属器件特征的横向尺寸。 通过选择性地横向氧化覆盖在电介质层上的器件特征的金属组合物进行氧化过程。 横向氧化工艺在器件特征上形成金属氧化物侧壁间隔物。 氧化工艺完成后，去除金属氧化物侧壁间隔物，剩下残留的未氧化金属层。 残余层的横向尺寸可以显着小于通过光学平版印刷技术实现的尺寸。

公开(公告)号：US06255169B1

公开(公告)日：2001-07-03

申请号：US09255053

申请日：1999-02-22

Applicant: Xiao-Yu Li ,  Qi Xiang ,  Sunil D. Mehta

Inventor： Xiao-Yu Li ,  Qi Xiang ,  Sunil D. Mehta

IPC: H01L218247

CPC classification number: H01L27/11521 ,  H01L27/11558

Abstract: A process for fabricating a non-volatile memory device includes the step of forming a nitrogen region in a semiconductor substrate prior to carrying out a thermal oxidation process to form a tunnel oxide layer. In a preferred process, nitrogen atoms are ion implanted into a silicon substrate to form a nitrogen region at the substrate surface. Then, a thermal oxidation process is carried out to grow a thin tunnel oxide layer overlying the surface of the nitrogen region. During the oxidation process, nitrogen is incorporated into the growing tunnel oxide layer. A floating-gate electrode is formed overlying the tunnel oxide layer and receives electrical charge transferred from a charge control region of the substrate through the tunnel oxide layer. The tunnel oxide layer is capable of undergoing repeated programming and erasing operations while exhibiting reduced effects from stress induced current leakage. In another aspect of the invention, an MOS transistor having enhanced carrier mobility is obtained by forming a gate oxide layer over a nitrogen region of a silicon substrate. The thermal oxidation process of the invention also provides both tunnel oxide layers and gate oxide layers having a reduced thickness for a given set of thermal oxidation conditions.

Abstract translation: 一种用于制造非易失性存储器件的方法包括在进行热氧化工艺以形成隧道氧化物层之前在半导体衬底中形成氮区的步骤。 在优选的方法中，将氮原子离子注入到硅衬底中以在衬底表面形成氮区。 然后，进行热氧化处理，以生长覆盖在氮区域的表面上的薄的隧道氧化物层。 在氧化过程中，将氮气掺入生长的隧道氧化物层中。 在隧道氧化物层上形成浮栅电极，并接收通过隧道氧化物层从衬底的电荷控制区转移的电荷。 隧道氧化物层能够经受重复的编程和擦除操作，同时表现出应力感应电流泄漏的减小的影响。 在本发明的另一方面，通过在硅衬底的氮区上形成栅极氧化层，获得具有增强的载流子迁移率的MOS晶体管。 本发明的热氧化方法还为给定的一组热氧化条件提供具有减小的厚度的隧道氧化物层和栅极氧化物层。