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公开(公告)号：US11829307B2
公开(公告)日：2023-11-28
申请号：US17568645
申请日：2022-01-04
Applicant: Rambus Inc.
Inventor： Liji Gopalakrishnan , Frederick A. Ware , Brent S. Haukness
CPC classification number: G06F13/1668 , G06F3/0604 , G06F3/0647 , G06F3/0659 , G06F3/0673
Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory device is disclosed. The memory device includes an array of storage cells and command interface circuitry to receive an internal transfer command. In response to the internal transfer command, transfer logic reads data from a first portion of the array of storage cells, transfers the data as on-chip transfer data, and writes the on-chip transfer data to a second portion of the array of storage cells. In response to the command interface circuitry receiving an interrupt command, the transfer logic pauses the internal transfer operation, and carries out an unrelated memory access operation involving at least the first portion of the array of storage cells or the second portion of the array of storage cells.
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公开(公告)号：US11487617B2
公开(公告)日：2022-11-01
申请号：US17106663
申请日：2020-11-30
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Brent S. Haukness , Lawrence Lai
Abstract: A memory component internally generates and stores the check bits of error detect and correct code (EDC). In a first mode, during a read transaction, the check bits are sent to the memory controller along with the data on the data mask (DM) signal lines. In a second mode, an unmasked write transaction is defined where the check bits are sent to the memory component on the data mask signal lines. In a third mode, a masked write transaction is defined where at least a portion of the check bits are sent from the memory controller on the data signal lines coincident with an asserted data mask signal line. By sending the check bits along with the data, the EDC code can be used to detect and correct errors that occur between the memory component and the memory controller.
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公开(公告)号：US20220342783A1
公开(公告)日：2022-10-27
申请号：US17744347
申请日：2022-05-13
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Brent S. Haukness , John Eric Linstadt , Scott C. Best
IPC: G06F11/20 , G11C11/4093 , G11C29/52
Abstract: A memory module is disclosed. The memory module includes a substrate, and respective first, second and third memory devices. The first memory device is of a first type disposed on the substrate and has addressable storage locations. The second memory device is also of the first type, and includes storage cells dedicated to store failure address information associated with defective storage locations in the first memory device. The third memory device is of the first type and includes storage cells dedicated to substitute as storage locations for the defective storage locations.
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公开(公告)号：US20220261361A1
公开(公告)日：2022-08-18
申请号：US17568645
申请日：2022-01-04
Applicant: Rambus Inc.
Inventor： Liji Gopalakrishnan , Frederick A. Ware , Brent S. Haukness
Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory device is disclosed. The memory device includes an array of storage cells and command interface circuitry to receive an internal transfer command. In response to the internal transfer command, transfer logic reads data from a first portion of the array of storage cells, transfers the data as on-chip transfer data, and writes the on-chip transfer data to a second portion of the array of storage cells. In response to the command interface circuitry receiving an interrupt command, the transfer logic pauses the internal transfer operation, and carries out an unrelated memory access operation involving at least the first portion of the array of storage cells or the second portion of the array of storage cells.
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公开(公告)号：US11068388B2
公开(公告)日：2021-07-20
申请号：US16584827
申请日：2019-09-26
Applicant: Rambus Inc.
Inventor： Ian Shaeffer , Brent S. Haukness
Abstract: A method of programming data into a memory device including an array of memory cells is disclosed. The method comprises receiving at least one program command that addresses a number of the memory cells for a programming operation to program data in the memory cells. The at least one program command is executed by iteratively carrying out at least one program/verify cycle to incrementally program the addressed memory cells with the program data. A secondary command may be selectively received after initiating but before completing the programming operation. The programming operation may be selectively resumed by first verifying the memory cells, then carrying out at least one program/verify cycle.
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Patent Agency Ranking
公开(公告)号：US10861554B2
公开(公告)日：2020-12-08
申请号：US15956647
申请日：2018-04-18
Applicant: Rambus Inc.
Inventor： Brent S. Haukness , Ian Shaeffer , Gary Bela Bronner
Abstract: A memory system includes an array of non-volatile memory cells and a memory controller having a first port to receive a program command that addresses a number of the memory cells for a programming operation, having a second port coupled to the memory array via a command pipeline, and configured to create a plurality of fractional program commands in response to the program command. Execution of each fractional program command applies a single program pulse to the addressed memory cells to incrementally program the addressed memory cells with program data, where the duration of the program pulse associated with each fractional program command is a selected fraction of the total programming time typically required to program the memory cells.
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公开(公告)号：US20180301194A1
公开(公告)日：2018-10-18
申请号：US15956647
申请日：2018-04-18
Applicant: Rambus Inc.
Inventor： Brent S. Haukness , Ian Shaeffer , Gary Bela Bronner
Abstract: A memory system includes an array of non-volatile memory cells and a memory controller having a first port to receive a program command that addresses a number of the memory cells for a programming operation, having a second port coupled to the memory array via a command pipeline, and configured to create a plurality of fractional program commands in response to the program command. Execution of each fractional program command applies a single program pulse to the addressed memory cells to incrementally program the addressed memory cells with program data, where the duration of the program pulse associated with each fractional program command is a selected fraction of the total programming time typically required to program the memory cells.
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公开(公告)号：US09823966B1
公开(公告)日：2017-11-21
申请号：US14527422
申请日：2014-10-29
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Brent S. Haukness , Lawrence Lai
CPC classification number: G06F11/1076 , G06F11/1048
Abstract: A memory component internally generates and stores the check bits of error detect and correct code (EDC). In a first mode, during a read transaction, the check bits are sent to the memory controller along with the data on the data mask (DM) signal lines. In a second mode, an unmasked write transaction is defined where the check bits are sent to the memory component on the data mask signal lines. In a third mode, a masked write transaction is defined where at least a portion of the check bits are sent from the memory controller on the data signal lines coincident with an asserted data mask signal line. By sending the check bits along with the data, the EDC code can be used to detect and correct errors that occur between the memory component and the memory controller.
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公开(公告)号：US09490002B2
公开(公告)日：2016-11-08
申请号：US14801558
申请日：2015-07-16
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Brent S. Haukness , Scott C. Best , Gary B. Bronner
IPC: G11C7/00 , G11C11/406
CPC classification number: G11C11/40611 , G11C2211/4061
Abstract: N out of every M number of refresh commands are ignored (filtered out) by a buffer chip on a memory module. N and M are programmable. The buffer receives refresh commands (e.g., auto-refresh commands) from the command-address channel, but does not issue a proportion of these commands to the DRAMs on the module. This reduces the power consumed by refresh operations. The buffer may replace some auto-refresh (REF) commands with activate (ACT) and precharge (PRE) commands directed to specific rows. These rows may have known ‘weak’ cells that require refreshing more often than a majority of the other rows on the module (or component). By ignoring some auto-refresh commands, and directing some others to specific rows that have ‘weak’ cells, the power consumed by refresh operations can be reduced.
Abstract translation: 每个M个刷新命令中的N个被存储器模块上的缓冲器芯片忽略（滤除掉）。 N和M是可编程的。 缓冲器从命令地址信道接收刷新命令（例如，自动刷新命令），但不向模块上的DRAM发出这些命令的一部分。 这减少了刷新操作所消耗的功耗。 缓冲区可以用针对特定行的激活（ACT）和预充电（PRE）命令替换一些自动刷新（REF）命令。 这些行可能具有比模块（或组件）上的大多数其他行更频繁刷新的已知“弱”单元格。 通过忽略一些自动刷新命令，并将一些其他命令指向具有“弱”单元格的特定行，可以减少刷新操作消耗的功率。
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公开(公告)号：US20150248327A1
公开(公告)日：2015-09-03
申请号：US14631570
申请日：2015-02-25
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Brent S. Haukness , John Eric Linstadt , Scott C. Best
CPC classification number: G06F11/1048 , G11C5/04 , G11C29/42 , G11C29/44 , G11C2029/0411 , G11C2029/4402
Abstract: A memory module is disclosed. The memory module includes a substrate, and respective first, second and third memory devices. The first memory device is of a first type disposed on the substrate and has addressable storage locations. The second memory device is also of the first type, and includes storage cells dedicated to store failure address information associated with defective storage locations in the first memory device. The third memory device is of the first type and includes storage cells dedicated to substitute as storage locations for the defective storage locations.
Abstract translation: 公开了一种存储器模块。 存储器模块包括衬底以及相应的第一，第二和第三存储器件。 第一存储器件是第一类型，其设置在衬底上并且具有可寻址的存储位置。 第二存储器件也是第一类型，并且包括专用于存储与第一存储器件中的不良存储位置相关联的故障地址信息的存储单元。 第三存储器件是第一类型的，并且包括专用于替换为存储位置不良的存储单元的存储单元。
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