公开(公告)号：US20230333989A1

公开(公告)日：2023-10-19

申请号：US18139220

申请日：2023-04-25

Applicant: Rambus Inc.

Inventor： Evan Lawrence Erickson ,  Christopher Haywood ,  Mark D. Kellam

IPC: G06F12/1009 ,  G06F13/16 ,  G06F12/0804 ,  G06F12/123 ,  G06F12/0882

CPC classification number: G06F12/1009 ,  G06F13/1668 ,  G06F12/0804 ,  G06F12/123 ,  G06F12/0882 ,  G06F2212/7201

Abstract: Memory pages are background-relocated from a low-latency local operating memory of a server computer to a higher-latency memory installation that enables high-resolution access monitoring and thus access-demand differentiation among the relocated memory pages. Higher access-demand memory pages are background-restored to the low-latency operating memory, while lower access-demand pages are maintained in the higher latency memory installation and yet-lower access-demand pages are optionally moved to yet higher-latency memory installation.

公开(公告)号：US20230325540A1

公开(公告)日：2023-10-12

申请号：US18130362

申请日：2023-04-03

Applicant: Rambus Inc.

Inventor： Evan Lawrence Erickson ,  John Eric Linstadt

IPC: G06F21/79 ,  G06F21/85 ,  G06F21/60

CPC classification number: G06F21/79 ,  G06F21/85 ,  G06F21/602

Abstract: A buffer integrated circuit (IC) chip is disclosed. The buffer IC chip includes host interface circuitry to receive a request from at least one host. The request includes at least one command to access a memory. Memory interface circuitry couples to the memory. Message authentication circuitry performs a verification operation on the received request. Selective containment circuitry, during a containment mode of operation, (1) inhibits changes to the memory in response to the at least one command until completion of the verification operation, and (2) during performance of the verification operation, carries out at least one non-memory modifying sub-operation associated with the at least one command.

公开(公告)号：US20230305891A1

公开(公告)日：2023-09-28

申请号：US18094474

申请日：2023-01-09

Applicant: Rambus Inc.

Inventor： Christopher Haywood ,  Evan Lawrence Erickson

IPC: G06F9/50 ,  G06F9/451 ,  G06F12/02 ,  G06F12/1009 ,  G06F12/1072

CPC classification number: G06F9/5016 ,  G06F9/452 ,  G06F9/5077 ,  G06F12/0238 ,  G06F12/1009 ,  G06F12/1072 ,  G06F2212/7201

Abstract: A memory allocation device for deployment within a host server computer includes control circuitry, a first interface to a local processing unit disposed within the host computer and local operating memory disposed within the host computer, and a second interface to a remote computer. The control circuitry allocates a first portion of the local memory to a first process executed by the local processing unit and transmits, to the remote computer via the second interface, a request to allocate to a second process executed by the local processing unit a first portion of a remote memory disposed within the remote computer. The control circuitry further receives instructions via the first interface to store data at a memory address within the first portion of the remote memory and transmits those instructions to the remote computer via the second interface.

公开(公告)号：US11567679B2

公开(公告)日：2023-01-31

申请号：US17333409

申请日：2021-05-28

Applicant: Rambus Inc.

Inventor： Evan Lawrence Erickson ,  Christopher Haywood

IPC: G06F3/06

Abstract: A memory allocation device on an originating node requests an allocation of memory from a remote node. In response, the memory allocation device on the remote node returns a global system address that can be used to access the remote allocation from the originating node. Concurrent with the memory allocation device assigning (associating) a local (to its node) physical address to be used to access the remote allocation, the remote node allocates local physical memory to fulfill the remote allocation request. In this manner, the remote node has already completed the overhead operations associated with the remote allocation requested by the time the remote allocation is accessed by the originating node.

公开(公告)号：US11561834B2

公开(公告)日：2023-01-24

申请号：US16743271

申请日：2020-01-15

Applicant: Rambus Inc.

Inventor： Joseph James Tringali ,  Jianbing Chen ,  Evan Lawrence Erickson ,  Keith Lowrey

IPC: G06F9/50 ,  G06F9/54 ,  G06F12/02 ,  G06N20/00 ,  G06F11/30

Abstract: Described are self-learning systems and methods for adaptive management of memory resources within a memory hierarchy. Memory allocations associated with different active functions are organized into blocks for placement in alternative levels in a memory hierarchy optimized for different metrics of e.g. cost and performance. A host processor monitors a performance metric of the active functions, such as the number of instructions per clock cycle, and reorganizes the function-specific blocks among the levels of the hierarchy. Over time, this process tends toward block organizations that improve the performance metric.

公开(公告)号：US20220179799A1

公开(公告)日：2022-06-09

申请号：US17543449

申请日：2021-12-06

Applicant: Rambus Inc.

Inventor： Evan Lawrence Erickson ,  Christopher Haywood ,  Mark D. Kellam

IPC: G06F12/1009 ,  G06F12/0882 ,  G06F12/0804 ,  G06F12/123 ,  G06F13/16

Abstract: Memory pages are background-relocated from a low-latency local operating memory of a server computer to a higher-latency memory installation that enables high-resolution access monitoring and thus access-demand differentiation among the relocated memory pages. Higher access-demand memory pages are background-restored to the low-latency operating memory, while lower access-demand pages are maintained in the higher latency memory installation and yet-lower access-demand pages are optionally moved to yet higher-latency memory installation.

公开(公告)号：US20210132999A1

公开(公告)日：2021-05-06

申请号：US17084392

申请日：2020-10-29

Applicant: Rambus Inc.

Inventor： Christopher Haywood ,  Evan Lawrence Erickson

IPC: G06F9/50 ,  G06F9/451 ,  G06F12/1072 ,  G06F12/02 ,  G06F12/1009

Abstract: A memory allocation device for deployment within a host server computer includes control circuitry, a first interface to a local processing unit disposed within the host computer and local operating memory disposed within the host computer, and a second interface to a remote computer. The control circuitry allocates a first portion of the local memory to a first process executed by the local processing unit and transmits, to the remote computer via the second interface, a request to allocate to a second process executed by the local processing unit a first portion of a remote memory disposed within the remote computer. The control circuitry further receives instructions via the first interface to store data at a memory address within the first portion of the remote memory and transmits those instructions to the remote computer via the second interface.

公开(公告)号：US20130279280A1

公开(公告)日：2013-10-24

申请号：US13865110

申请日：2013-04-17

Applicant: RAMBUS INC.

Inventor： Paul Damian Franzon ,  Evan Lawrence Erickson ,  Thomas Vogelsang ,  Frederick A. Ware

IPC: G11C29/04

CPC classification number: G11C29/04 ,  G11C29/702 ,  G11C29/808

Abstract: A memory device includes a stack of circuit layers, each circuit layer having formed thereon a memory circuit configured to store data and a redundant resources circuit configured to provide redundant circuitry to correct defective circuitry on at least one memory circuit formed on at least one layer in the stack. The redundant resources circuit includes a partial bank of redundant memory cells, wherein an aggregation of the partial bank of redundant memory cells in each of the circuit layers of the stack includes at least one full bank of redundant memory cells and wherein the redundant resources circuit is configured to replace at least one defective bank of memory cells formed on any of the circuit layers in the stack with at least a portion of the partial bank of redundant memory cells formed on any of the circuit layers in the stack.

Abstract translation: 存储器件包括电路层堆叠，每个电路层上形成有存储器电路，其被配置为存储数据，冗余资源电路被配置为提供冗余电路以校正在至少一个层上形成的至少一个存储器电路上的有缺陷的电路 堆栈。 所述冗余资源电路包括冗余存储器单元的部分组，其中所述堆叠的每个电路层中的冗余存储器单元的部分组的聚集包括至少一个全部冗余存储器单元，并且其中所述冗余资源电路为 被配置为替换形成在堆叠中的任何电路层上的至少一个存储单元的至少一个有缺陷的存储单元组，其中所述冗余存储器单元的部分库的至少一部分形成在堆叠中的任何电路层上。

公开(公告)号：US20250053521A1

公开(公告)日：2025-02-13

申请号：US18786296

申请日：2024-07-26

Applicant: Rambus Inc.

Inventor： Evan Lawrence Erickson

IPC: G06F13/16 ,  G06F12/02 ,  G06F13/42

Abstract: A memory system selectively compresses and/or decompresses pages of a memory array based on requests from a host device. Upon performing compression, the memory buffer device returns compression context metadata to the host device for storing in the page table of the host device to enable the host device to subsequently obtain data from the compressed page. The host device may subsequently send a request for the memory buffer device to perform decompression to a free page in the memory array for accessing by the host device, or the host device may directly access the compressed page for local decompression and storage.

公开(公告)号：US12174749B2

公开(公告)日：2024-12-24

申请号：US17576398

申请日：2022-01-14

Applicant: Rambus Inc.

Inventor： Steven C. Woo ,  Christopher Haywood ,  Evan Lawrence Erickson

IPC: G06F12/10 ,  G06F9/455 ,  G06F12/02 ,  G06F12/0882 ,  G06F12/1009

Abstract: The creation, maintenance, and accessing of page tables is done by a virtual machine monitor running on a computing system rather than the guest operating systems. This allows page table walks to be completed in fewer memory accesses when compared to the guest operating system's maintenance of the page tables. In addition, the virtual machine monitor may utilize additional resources to offload page table access and maintenance functions from the CPU to another device, such as a page table management device or page table management node. Offloading some or all page table access and maintenance functions to a specialized device or node enables the CPU to perform other tasks during page table walks and/or other page table maintenance functions.