公开(公告)号：US09954489B2

公开(公告)日：2018-04-24

申请号：US15632045

申请日：2017-06-23

Applicant: Rambus Inc.

Inventor： Masum Hossain ,  Farshid Aryanfar ,  Mohammad Hekmat ,  Reza Navid

IPC: H03B19/00 ,  G06F1/08 ,  H03L7/099 ,  H03K3/03 ,  H03K5/00 ,  G06F1/10

CPC classification number: H03B19/00 ,  G06F1/08 ,  G06F1/10 ,  H03K3/0315 ,  H03K5/00006 ,  H03L7/099

Abstract: Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.

公开(公告)号：US20180019706A1

公开(公告)日：2018-01-18

申请号：US15632045

申请日：2017-06-23

Applicant: Rambus Inc.

Inventor： Masum Hossain ,  Farshid Aryanfar ,  Mohammad Hekmat ,  Reza Navid

IPC: H03B19/00 ,  H03K3/03 ,  G06F1/08 ,  G06F1/10 ,  H03L7/099 ,  H03K5/00

CPC classification number: H03B19/00 ,  G06F1/08 ,  G06F1/10 ,  H03K3/0315 ,  H03K5/00006 ,  H03L7/099

Abstract: Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.

公开(公告)号：US20170331483A1

公开(公告)日：2017-11-16

申请号：US15605932

申请日：2017-05-25

Applicant: Rambus Inc.

Inventor： Masum Hossain ,  Farshid Aryanfar

IPC: H03L7/23 ,  H03L7/18 ,  H03L7/099 ,  H03L7/081 ,  H03L7/08

CPC classification number: H03L7/235 ,  H03L7/0805 ,  H03L7/081 ,  H03L7/099 ,  H03L7/0995 ,  H03L7/18 ,  H03L7/23

Abstract: A frequency synthesizer generates a wide range of frequencies from a single oscillator while achieving good noise performance. A cascaded phase-locked loop (PLL) circuit includes a first PLL circuit with an LC voltage controlled oscillator (VCO) and a second PLL circuit with a ring VCO. A feedforward path from the first PLL circuit to the second PLL circuit provides means and signal path for cancellation of phase noise, thereby reducing or eliminating spur and quantization effects. The frequency synthesizer can directly generate in-phase and quadrature phase output signals. A split-tuned ring-based VCO is controlled via a phase error detection loop to reduce or eliminate phase error between the quadrature signals.

公开(公告)号：US20160241191A1

公开(公告)日：2016-08-18

申请号：US15049517

申请日：2016-02-22

Applicant: Rambus Inc.

Inventor： Mohammad Hekmat ,  Farshid Aryanfar ,  Kambiz Kaviani

IPC: H03B27/00 ,  H01F27/28 ,  H03B15/00 ,  H03K5/145 ,  H03B5/12

CPC classification number: H03B27/00 ,  H01F27/006 ,  H01F27/2804 ,  H03B5/1212 ,  H03B5/1215 ,  H03B5/1228 ,  H03B15/00 ,  H03K5/145 ,  H03K5/24 ,  H03K2005/00052

Abstract: Coupled multi-inductors and their applications. An apparatus includes several circuit stages. Each circuit stage includes an inductive element that overlaps with the inductive elements of its adjacent circuit stages, forming a loop of coupled circuit stages. The apparatus may be, for example, a multi-phase oscillator with multiple oscillators that are magnetically coupled to each other for generating oscillation signals at different phases. The apparatus may also be, for example, a phase interpolator for combining input signals.

Abstract translation: 耦合多电感及其应用。 一种装置包括几个电路级。 每个电路级包括与其相邻电路级的电感元件重叠的电感元件，形成耦合电路级的回路。 该装置可以是例如具有彼此磁耦合的多个振荡器的多相振荡器，用于在不同相位产生振荡信号。 该装置也可以是例如用于组合输入信号的相位插值器。

公开(公告)号：US20150365095A1

公开(公告)日：2015-12-17

申请号：US14746618

申请日：2015-06-22

Applicant: Rambus Inc.

Inventor： Masum Hossain ,  Farshid Aryanfar

IPC: H03L7/23 ,  H03L7/099 ,  H03L7/081

CPC classification number: H03L7/235 ,  H03L7/0805 ,  H03L7/081 ,  H03L7/099 ,  H03L7/0995 ,  H03L7/18 ,  H03L7/23

Abstract: A frequency synthesizer generates a wide range of frequencies from a single oscillator while achieving good noise performance. A cascaded phase-locked loop (PLL) circuit includes a first PLL circuit with an LC voltage controlled oscillator (VCO) and a second PLL circuit with a ring VCO. A feedforward path from the first PLL circuit to the second PLL circuit provides means and signal path for cancellation of phase noise, thereby reducing or eliminating spur and quantization effects. The frequency synthesizer can directly generate in-phase and quadrature phase output signals. A split-tuned ring-based VCO is controlled via a phase error detection loop to reduce or eliminate phase error between the quadrature signals.

Abstract translation: 频率合成器从单个振荡器产生宽范围的频率，同时实现良好的噪声性能。 级联锁相环（PLL）电路包括具有LC压控振荡器（VCO）的第一PLL电路和具有环形VCO的第二PLL电路。 从第一PLL电路到第二PLL电路的前馈路径提供用于消除相位噪声的装置和信号路径，从而减少或消除杂散和量化效应。 频率合成器可以直接产生同相和正交相输出信号。 通过相位误差检测回路来控制分频环形VCO，以减少或消除正交信号之间的相位误差。

公开(公告)号：US20140347092A1

公开(公告)日：2014-11-27

申请号：US14368772

申请日：2012-12-22

Applicant: Rambus Inc.

Inventor： Amir Amirkhany ,  Farshid Aryanfar ,  Ravindranath Kollipara ,  Xingchao (Chuck) Yuan

IPC: H03K19/00

CPC classification number: H03K19/0005 ,  G06F13/4086 ,  G11C29/50008 ,  H03K19/017545 ,  H04L25/0278

Abstract: Alternating on-die termination impedances are applied within an integrated circuit device to up-convert signal reflections to higher frequencies that are attenuated by the signaling channel as the reflections propagate toward an intended signal receiver. Through this approach, the disruptive effect of reflected signals may be significantly reduced with relatively little overhead within the interconnected integrated circuit devices and little or no change to the printed circuit board or other interconnect medium. Changes to the printed circuit board or other interconnect medium can be made to further increase attenuation over the frequency band of the up-converted reflection and outside of the transmission band of signals of interest.

Abstract translation: 在集成电路器件内施加交替的片上终端阻抗，以将信号反射上变频到由信号通道衰减的较高频率，因为反射向预期信号接收器传播。 通过这种方法，相互连接的集成电路器件内的相对较少的开销可以显着降低反射信号的破坏性影响，并且对印刷电路板或其它互连介质几乎没有或没有改变。 可以对印刷电路板或其它互连介质进行改变，以进一步增加在上变频反射的频带和感兴趣的信号的传输频带之外的衰减。

公开(公告)号：US20140323223A1

公开(公告)日：2014-10-30

申请号：US14331144

申请日：2014-07-14

Applicant: Rambus Inc.

Inventor： Yu Ju Chen ,  Farshid Aryanfar ,  Carl W. Werner

IPC: A63F13/30

CPC classification number: A63F13/235 ,  A63F13/213 ,  A63F13/843 ,  A63F2300/1006 ,  A63F2300/1031 ,  A63F2300/403 ,  A63F2300/8088 ,  G06F3/0346 ,  G06F3/038 ,  G06F2203/0384

Abstract: A method of communicating data between a game console unit and at least one wireless mobile game controller is disclosed. The method includes establishing an uplink from the at least one mobile game controller to the game console unit via a first millimeter-wave wireless link, and establishing a downlink from the game console unit to the at least one wireless mobile game controller via a second millimeter wave wireless link.

Abstract translation: 公开了一种在游戏控制台单元与至少一个无线移动游戏控制器之间传送数据的方法。 该方法包括经由第一毫米波无线链路从至少一个移动游戏控制器建立到游戏控制台单元的上行链路，以及经由第二毫米从游戏控制台单元向至少一个无线移动游戏控制器建立下行链路 波无线连接。