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    TIMING-DRIFT CALIBRATION
    22.
    发明申请
    TIMING-DRIFT CALIBRATION 有权
    时序移位校准

    公开(公告)号：US20160035437A1

    公开(公告)日：2016-02-04

    申请号：US14884601

    申请日：2015-10-15

    Applicant: RAMBUS INC.

    Inventor： Yohan U. Frans ,  Wayne F. Ellis ,  Akash Bansal

    IPC: G11C29/50 ,  G11C7/22

    CPC classification number: G11C29/50012 ,  G01R23/02 ,  G01R23/15 ,  G01R35/005 ,  G06F1/08 ,  G06F1/12 ,  G06F11/1604 ,  G06F13/1689 ,  G11C7/04 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/18 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254 ,  H03L1/02

    Abstract: The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit.

    Abstract translation: 所公开的实施例涉及支持定时漂移校准的存储器系统的组件。 在具体实施例中，该存储器系统包含存储器件（或多个器件），其包括可产生频率的时钟分配电路和振荡器电路，其中频率变化表示时钟分配电路的定时漂移。 存储器件还包括测量电路，其被配置为测量振荡器电路的频率。

    TIMING-DRIFT CALIBRATION
    23.
    发明申请
    TIMING-DRIFT CALIBRATION 有权
    时序移位校准

    公开(公告)号：US20150131398A1

    公开(公告)日：2015-05-14

    申请号：US14601078

    申请日：2015-01-20

    Applicant: RAMBUS INC.

    Inventor： Yohan U. Frans ,  Wayne F. Ellis ,  Akash Bansal

    IPC: G11C8/18 ,  G11C7/22

    CPC classification number: G11C29/50012 ,  G01R23/02 ,  G01R23/15 ,  G01R35/005 ,  G06F1/08 ,  G06F1/12 ,  G06F11/1604 ,  G06F13/1689 ,  G11C7/04 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/18 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254 ,  H03L1/02

    Abstract: The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit. Additionally, the memory system contains a memory controller which can transmit a request to the memory device to trigger the memory device to measure the frequency of the oscillator circuit. The memory controller is also configured to receive the measured frequency from the memory device and uses the measured frequency to determine the timing drift in the memory device.

    Abstract translation: 所公开的实施例涉及支持定时漂移校准的存储器系统的组件。 在具体实施例中，该存储器系统包含存储器件（或多个器件），其包括可产生频率的时钟分配电路和振荡器电路，其中频率变化表示时钟分配电路的定时漂移。 存储装置还包括被配置为测量振荡器电路的频率的测量电路。 此外，存储器系统包含存储器控制器，该存储器控制器可向存储器件发送请求以触发存储器件以测量振荡器电路的频率。 存储器控制器还被配置为从存储器件接收测量的频率，并使用测量的频率来确定存储器件中的定时漂移。

    PROTOCOL FOR MEMORY POWER-MODE CONTROL
    29.
    发明申请
    PROTOCOL FOR MEMORY POWER-MODE CONTROL 有权
    用于存储器功率模式控制的协议

    公开(公告)号：US20150103610A1

    公开(公告)日：2015-04-16

    申请号：US14573323

    申请日：2014-12-17

    Applicant: Rambus Inc.

    Inventor： Wayne F. Ellis ,  Wayne S. Richardson ,  Akash Bansal ,  Frederick A. Ware ,  Lawrence Lai ,  Kishore Ven Kasamsetty

    IPC: G11C11/406 ,  G11C11/4074

    CPC classification number: G11C11/40615 ,  G06F1/3234 ,  G11C7/02 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074 ,  G11C29/022 ,  G11C29/028

    Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

    Abstract translation: 在一个实施例中，存储器设备包括存储器核心和用于接收命令和数据的输入接收器。 存储器装置还包括寄存器，用于存储指示输入接收器的子集是否响应于控制信号掉电的值。 存储器控制器将命令和数据发送到存储器件。 存储器控制器还发送该值以指示存储器件的输入接收器的子集是否响应于控制信号掉电。 此外，响应于自我新命令，存储装置延迟进入自刷新操作，直到接收到接收到自刷新命令后接收的控制信号为止。

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