公开(公告)号：US10102081B2

公开(公告)日：2018-10-16

申请号：US15401985

申请日：2017-01-09

Applicant: Rambus Inc.

Inventor： Shih-ho Wu ,  Christopher Haywood

IPC: G06F11/14 ,  G11C14/00 ,  G06F3/06 ,  G06F11/16

Abstract: The present invention is directed to computer storage systems and methods thereof. More specifically, embodiments of the present invention provide an isolated storage control system that includes both a non-volatile memory and a volatile memory. The non-volatile memory comprises a data area and a metadata area. In power failure or similar situations, content of the volatile memory is copied to the data area of the non-volatile memory, and various system parameters are stored at the metadata area. When the system restores its operation, the information at the metadata area is processed, and the content stored at the data area of the non-volatile memory is copied to the volatile memory. There are other embodiments as well.

公开(公告)号：US20250087255A1

公开(公告)日：2025-03-13

申请号：US18895130

申请日：2024-09-24

Applicant: Rambus Inc.

Inventor： Christopher Haywood ,  Steven C. Woo

IPC: G11C7/10

Abstract: A memory system includes a memory controller, a plurality of serial data buffers, and a plurality of memory devices. The memory controller issues packetized commands and data to the serial data buffers. The serial data buffers each apply a different remapping function to remap an input command address in the packetized commands to respective remapped memory addresses that are different for each serial data buffer. The serial data buffers then issue commands to the memory devices using the remapped addresses. The remapping functions may be designed to mitigate row hammer effects. The serial data buffers may furthermore apply transformations to read and write data to facilitate encryption and decryption.

公开(公告)号：US12174749B2

公开(公告)日：2024-12-24

申请号：US17576398

申请日：2022-01-14

Applicant: Rambus Inc.

Inventor： Steven C. Woo ,  Christopher Haywood ,  Evan Lawrence Erickson

IPC: G06F12/10 ,  G06F9/455 ,  G06F12/02 ,  G06F12/0882 ,  G06F12/1009

Abstract: The creation, maintenance, and accessing of page tables is done by a virtual machine monitor running on a computing system rather than the guest operating systems. This allows page table walks to be completed in fewer memory accesses when compared to the guest operating system's maintenance of the page tables. In addition, the virtual machine monitor may utilize additional resources to offload page table access and maintenance functions from the CPU to another device, such as a page table management device or page table management node. Offloading some or all page table access and maintenance functions to a specialized device or node enables the CPU to perform other tasks during page table walks and/or other page table maintenance functions.

公开(公告)号：US12125556B2

公开(公告)日：2024-10-22

申请号：US17897439

申请日：2022-08-29

Applicant: Rambus Inc.

Inventor： Christopher Haywood ,  Steven C. Woo

IPC: G11C7/10

CPC classification number: G11C7/1084 ,  G11C7/1012 ,  G11C7/109

Abstract: A memory system includes a memory controller, a plurality of serial data buffers, and a plurality of memory devices. The memory controller issues packetized commands and data to the serial data buffers. The serial data buffers each apply a different remapping function to remap an input command address in the packetized commands to respective remapped memory addresses that are different for each serial data buffer. The serial data buffers then issue commands to the memory devices using the remapped addresses. The remapping functions may be designed to mitigate row hammer effects. The serial data buffers may furthermore apply transformations to read and write data to facilitate encryption and decryption.

公开(公告)号：US11663138B2

公开(公告)日：2023-05-30

申请号：US17543449

申请日：2021-12-06

Applicant: Rambus Inc.

Inventor： Evan Lawrence Erickson ,  Christopher Haywood ,  Mark D. Kellam

IPC: G06F12/10 ,  G06F12/1009 ,  G06F13/16 ,  G06F12/0804 ,  G06F12/123 ,  G06F12/0882

CPC classification number: G06F12/1009 ,  G06F12/0804 ,  G06F12/0882 ,  G06F12/123 ,  G06F13/1668 ,  G06F2212/7201

Abstract: Memory pages are background-relocated from a low-latency local operating memory of a server computer to a higher-latency memory installation that enables high-resolution access monitoring and thus access-demand differentiation among the relocated memory pages. Higher access-demand memory pages are background-restored to the low-latency operating memory, while lower access-demand pages are maintained in the higher latency memory installation and yet-lower access-demand pages are optionally moved to yet higher-latency memory installation.

公开(公告)号：US11567803B2

公开(公告)日：2023-01-31

申请号：US17084392

申请日：2020-10-29

Applicant: Rambus Inc.

Inventor： Christopher Haywood ,  Evan Lawrence Erickson

IPC: G06F12/00 ,  G06F9/50 ,  G06F9/451 ,  G06F12/02 ,  G06F12/1009 ,  G06F12/1072

Abstract: A memory allocation device for deployment within a host server computer includes control circuitry, a first interface to a local processing unit disposed within the host computer and local operating memory disposed within the host computer, and a second interface to a remote computer. The control circuitry allocates a first portion of the local memory to a first process executed by the local processing unit and transmits, to the remote computer via the second interface, a request to allocate to a second process executed by the local processing unit a first portion of a remote memory disposed within the remote computer. The control circuitry further receives instructions via the first interface to store data at a memory address within the first portion of the remote memory and transmits those instructions to the remote computer via the second interface.

公开(公告)号：US20230022530A1

公开(公告)日：2023-01-26

申请号：US17860773

申请日：2022-07-08

Applicant: Rambus Inc.

Inventor： Christopher Haywood

IPC: G06F3/06

Abstract: A serial data buffer integrated circuit comprises unidirectional host-side input and output ports, and unidirectional memory-side input and output ports. Scheduling logic generates memory device commands for writing to and reading from a memory device based on a set of host-side input packets received from a memory controller. A unidirectional serial host side input port receives host-side input packets from the memory controller. A unidirectional serial memory side output port transmits the memory device commands and the write data to the memory device based on the scheduled timing. A unidirectional serial memory side input port receives read data from the memory device in response to a read command, and a unidirectional serial host side output port transmits the read data to the memory controller within the timing constraints of the memory device.

公开(公告)号：US11121904B2

公开(公告)日：2021-09-14

申请号：US15616779

申请日：2017-06-07

Applicant: Rambus Inc.

Inventor： Christopher Haywood

IPC: H04L29/08 ,  H04L12/24 ,  G06F13/40 ,  G06F13/28 ,  G06F13/42

Abstract: Embodiments of the present invention are directed to memories used in server applications. More specifically, embodiments of the present invention provide a server system has a memory management module that is connected to a processor, a memory module, and a network interface. The memory management module is configured to allocate a first channel to access the memory module for local memory accesses by the processor and communicate first data blocks between the memory module and the processor. The memory management module determines that an amount of memory in the memory module is insufficient for an amount of memory needed by the processor, to allocate a second channel between the memory management module and the network interface to access a second memory module over a network for remote memory accesses by the processor. The memory management module communicates second data blocks between the memory management module and the network interface.

公开(公告)号：US10430092B1

公开(公告)日：2019-10-01

申请号：US14444225

申请日：2014-07-28

Applicant: Rambus Inc.

Inventor： Shih-ho Wu ,  Christopher Haywood

IPC: G06F12/00 ,  G06F3/06 ,  G11C14/00 ,  G11C16/04

Abstract: The present invention is directed to computer storage systems and methods thereof. In an embodiment, a memory system comprises a controller module, a nonvolatile memory, and a volatile memory. The controller module operates according to a command and operation table. The command and operation table can be updated to change the way controller module operates. When the command and operation table is updated, the updated table is stored at a predefined location of the nonvolatile memory. There are other embodiments as well.

公开(公告)号：US09910612B2

公开(公告)日：2018-03-06

申请号：US15137802

申请日：2016-04-25

Applicant: Rambus Inc.

Inventor： Christopher Haywood

IPC: G06F3/06 ,  G06F13/16 ,  G11C7/10 ,  G06F12/06 ,  G06F13/42 ,  G11C14/00

CPC classification number: G06F3/0626 ,  G06F3/0604 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0685 ,  G06F3/0688 ,  G06F12/06 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/1694 ,  G06F13/4282 ,  G11C7/1072 ,  G11C14/0045

Abstract: The present memory system includes a memory buffer having an interface arranged to buffer data and/or command bytes being written to or read from the RAM chips residing on a DIMM by a host controller. The memory buffer further includes at least one additional interface arranged to buffer data and/or command bytes between the host controller or RAM chips and one or more external devices coupled to the at least one additional interface. For example, the memory buffer may include a SATA interface and be arranged to convey data between the host controller or RAM chips and FLASH memory devices coupled to the SATA interface. The memory buffer may be employed in various types of systems, such as a computer server system, a network system, or a data center.