公开(公告)号：US20170337143A1

公开(公告)日：2017-11-23

申请号：US15616785

申请日：2017-06-07

Applicant: Rambus Inc.

Inventor： Pravin Kumar Venkatesan ,  Liji Gopalakrishnan ,  Kashinath Prabhu ,  Makarand Shirasgaonkar

IPC: G06F13/16

CPC classification number: G06F13/1668 ,  Y02D10/14

Abstract: A transmitter is coupled to a command and address (CA) bus. The transmitter is configurable with dual-mode support to send commands over the CA bus in a first swing mode and a second swing mode. The transmitter is configurable to send a first command over the CA bus via the pins while in the first swing mode, initiate calibration of the master device to send commands over the CA bus in the second swing mode, and to send a second command over the CA bus via the pins while in the second swing mode.

公开(公告)号：US20150205751A1

公开(公告)日：2015-07-23

申请号：US14411723

申请日：2013-07-17

Applicant: Rambus Inc.

Inventor： Kyung Suk Oh ,  Pravin Kumar Venkatesan ,  Yohan Usthavia Frans

IPC: G06F13/42 ,  G06F13/28

CPC classification number: G06F13/4221 ,  G06F13/28 ,  H04L25/0278 ,  H04L25/0298 ,  Y02D10/14 ,  Y02D10/151

Abstract: A memory controller and/or memory device control termination of a communication link in order to achieve power savings while reducing or eliminating unwanted reflections in the channel. Following transmission of data over the communication channel, termination is left enabled for a programmable time period beginning immediately following completion of the transmission. The time period is sufficiently long to allow the unwanted reflections to be absorbed by the termination. Following the time period, the termination is disabled for power savings.

Abstract translation: 存储器控制器和/或存储器设备控制通信链路的终端，以便在减少或消除信道中的不必要的反射的同时实现功率节省。 在通过通信信道传输数据之后，在传输完成之后立即开始可编程时间段的终止。 该时间段足够长以允许不期望的反射被终端吸收。 在该时间段之后，终止功能被禁用以节省电力。

公开(公告)号：US20140149654A1

公开(公告)日：2014-05-29

申请号：US14086818

申请日：2013-11-21

Applicant: Rambus Inc.

Inventor： Pravin Kumar Venkatesan ,  Kashinath Prabhu ,  Makarand Shirasgaonkar ,  Wayne Dettloff

IPC: G11C11/406 ,  H03K3/012

CPC classification number: G11C29/023 ,  G11C5/147 ,  G11C7/04 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/4076 ,  G11C11/4099 ,  G11C29/021 ,  G11C29/028 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2207/2254 ,  H03M1/66

Abstract: A single-ended receiver includes an internal voltage generation circuit to set a first internal reference voltage (Vref). A model voltage generation circuit is configurable to receive an external reference voltage to be calibrated during an initial calibration. The model voltage generation circuit is configurable to track an offset value for voltage-temperature (VT) drift and the offset value is applied to the internal voltage generation circuit to calibrate the internal Vref during a periodic calibration of the single-ended receiver.

Abstract translation: 单端接收器包括用于设定第一内部参考电压（Vref）的内部电压产生电路。 模型电压发生电路可配置为在初始校准期间接收要校准的外部参考电压。 模型电压发生电路可配置为跟踪电压 - 温度（VT）漂移的偏移值，并且在单端接收器的周期性校准期间，将偏移值应用于内部电压产生电路以校准内部Vref。

公开(公告)号：US20250036581A1

公开(公告)日：2025-01-30

申请号：US18770876

申请日：2024-07-12

Applicant: Rambus Inc.

Inventor： Pravin Kumar Venkatesan ,  Liji Gopalakrishnan ,  Kashinath Ullhas Prabhu ,  Makarand Ajit Shirasgaonkar

IPC: G06F13/16

Abstract: A method of operation of a flash integrated circuit (IC) memory device is described. The flash IC memory device has an array of memory cells and an interface to receive control, address and data signals using an internal reference voltage. The method includes, at boot-up, initializing the internal reference voltage to a default voltage. At boot-up, the interface is operable to receive, using the internal reference voltage, signals having a first voltage swing at a first signaling frequency. The method includes receiving a first command that specifies calibration of the interface during a calibration mode. The calibration mode is used to calibrate the interface to operate at a second signaling frequency and receive signals having a second voltage swing. The second voltage swing is smaller than the first voltage swing and the second signaling frequency is higher than the first signaling frequency.

公开(公告)号：US11829308B2

公开(公告)日：2023-11-28

申请号：US18082446

申请日：2022-12-15

Applicant: Rambus Inc.

Inventor： Pravin Kumar Venkatesan ,  Liji Gopalakrishnan ,  Kashinath Ullhas Prabhu ,  Makarand Ajit Shirasgaonkar

IPC: G06F13/16

CPC classification number: G06F13/1668 ,  Y02D10/00

Abstract: A method of operation of a flash integrated circuit (IC) memory device is described. The flash IC memory device has an array of memory cells and an interface to receive control, address and data signals using an internal reference voltage. The method includes, at boot-up, initializing the internal reference voltage to a default voltage. At boot-up, the interface is operable to receive, using the internal reference voltage, signals having a first voltage swing at a first signaling frequency. The method includes receiving a first command that specifies calibration of the interface during a calibration mode. The calibration mode is used to calibrate the interface to operate at a second signaling frequency and receive signals having a second voltage swing. The second voltage swing is smaller than the first voltage swing and the second signaling frequency is higher than the first signaling frequency.

公开(公告)号：US20230052053A1

公开(公告)日：2023-02-16

申请号：US17849450

申请日：2022-06-24

Applicant: Rambus Inc.

Inventor： Pravin Kumar Venkatesan ,  Liji Gopalakrishnan ,  Kashinath Ullhas Prabhu ,  Makarand Ajit Shirasgaonkar

IPC: G06F13/16

Abstract: A single-ended receiver is coupled to an input-output (I/O) pin of a command and address (CA) bus. The receiver is configurable with dual-mode I/O support to operate the CA bus in a low-swing mode and a high-swing mode. The receiver is configurable to receive a first command on the I/O pin while in the high-swing mode, initiate calibration of the slave device to operate in the low-swing mode in response to the first command, switch the slave device to operate in the low-swing mode while the CA bus remains active, and to receive a second command on the I/O pin while in the low-swing mode.

公开(公告)号：US20190102327A1

公开(公告)日：2019-04-04

申请号：US16145837

申请日：2018-09-28

Applicant: Rambus Inc.

Inventor： Pravin Kumar Venkatesan ,  Liji Gopalakrishnan ,  Kashinath Ullhas Prabhu ,  Makarand Ajit Shirasgaonkar

IPC: G06F13/16

CPC classification number: G06F13/1668 ,  Y02D10/14

Abstract: A single-ended receiver is coupled to an input-output (I/O) pin of a command and address (CA) bus. The receiver is configurable with dual-mode I/O support to operate the CA bus in a low-swing mode and a high-swing mode. The receiver is configurable to receive a first command on the I/O pin while in the high-swing mode, initiate calibration of the slave device to operate in the low-swing mode in response to the first command, switch the slave device to operate in the low-swing mode while the CA bus remains active, and to receive a second command on the I/O pin while in the low-swing mode.

公开(公告)号：US09715467B2

公开(公告)日：2017-07-25

申请号：US14080724

申请日：2013-11-14

Applicant: RAMBUS INC.

Inventor： Pravin Kumar Venkatesan ,  Liji Gopalakrishnan ,  Kashinath Prabhu ,  Makarand Shirasgaonkar

IPC: G06F13/16

CPC classification number: G06F13/1668 ,  Y02D10/14

Abstract: A single-ended receiver is coupled to an input-output (I/O) pin of a command and address (CA) bus. The receiver is configurable with dual-mode I/O support to operate the CA bus in a low-swing mode and a high-swing mode. The receiver is configurable to receive a first command on the I/O pin while in the high-swing mode, initiate calibration of the slave device to operate in the low-swing mode in response to the first command, switch the slave device to operate in the low-swing mode while the CA bus remains active, and to receive a second command on the I/O pin while in the low-swing mode.