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93 条记录 (耗时 0.043 秒)

    Management of cache memory in a flash cache architecture
    23.
    发明授权
    Management of cache memory in a flash cache architecture 有权
    在闪存缓存架构中管理缓存内存

    公开(公告)号：US09135181B2

    公开(公告)日：2015-09-15

    申请号：US13280869

    申请日：2011-10-25

    申请人： Evangelos Stavros Eleftheriou ,  Robert Haas ,  Xiao-Yu Hu

    发明人： Evangelos Stavros Eleftheriou ,  Robert Haas ,  Xiao-Yu Hu

    IPC分类号： G06F13/00 ,  G06F13/28 ,  G06F12/08 ,  G06F12/02

    CPC分类号： G06F12/0888 ,  G06F12/0246

    摘要： A method for managing cache memory in a flash cache architecture. The method includes providing a storage cache controller, at least a flash memory comprising a flash controller, and at least a backend storage device, and maintaining read cache metadata for tracking on the flash memory cached data to be read, and write cache metadata for tracking on the flash memory data expected to be cached.

    摘要翻译： 一种用于在闪存缓存架构中管理高速缓存存储器的方法。 该方法包括提供存储高速缓存控制器，至少包括闪存控制器的闪速存储器，以及至少后端存储设备，并且维护读取高速缓存元数据，用于跟踪要读取的闪速存储器缓存的数据，以及写入用于跟踪的高速缓存元数据 闪存数据预计将被缓存。

    Data management in solid state storage systems
    24.
    发明授权
    Data management in solid state storage systems 有权
    固态存储系统中的数据管理

    公开(公告)号：US09037951B2

    公开(公告)日：2015-05-19

    申请号：US13516627

    申请日：2010-12-16

    申请人： Roy D. Cideciyan ,  Evangelos S. Eleftheriou ,  Robert Haas ,  Xiao-Yu Hu ,  Ilias Iliadas ,  Thomas Mittelholzer

    发明人： Roy D. Cideciyan ,  Evangelos S. Eleftheriou ,  Robert Haas ,  Xiao-Yu Hu ,  Ilias Iliadas ,  Thomas Mittelholzer

    IPC分类号： G06F11/10 ,  G11C29/00

    CPC分类号： G06F11/1008 ,  G06F11/1012 ,  G06F11/1068 ,  G06F11/108

    摘要： Methods and apparatus are provided for controlling data management operations including storage of data in solid state storage of a solid state storage system. Input data is stored in successive groups of data write locations in the solid state storage. Each group comprises a set of write locations in each of a plurality of logical subdivisions of the solid state storage. The input data to be stored in each group is encoded in accordance with first and second linear error correction codes. The encoding is performed by constructing from the input data to be stored in each group a logical array of rows and columns of data symbols. The rows and columns are respectively encoded in accordance with the first and second linear error correction codes to produce an encoded array in which all rows correspond to respective first codewords and columns correspond to respective second codewords.

    摘要翻译： 提供了用于控制数据管理操作的方法和装置，包括固态存储系统的固态存储中的数据的存储。 输入数据存储在固态存储器中的连续的数据写入位置组中。 每个组包括在固态存储器的多个逻辑子部分的每一个中的一组写入位置。 要存储在每个组中的输入数据根据第一和第二线性纠错码进行编码。 通过从输入数据中构成数据符号的行和列的逻辑阵列，来构成编码。 行和列分别根据第一和第二线性纠错码编码以产生编码阵列，其中所有行对应于相应的第一码字和列对应于相应的第二码字。

    DECODING OF LDPC CODE
    25.
    发明申请
    DECODING OF LDPC CODE 有权
    LDPC码的解码

    公开(公告)号：US20150052413A1

    公开(公告)日：2015-02-19

    申请号：US14358609

    申请日：2011-05-25

    申请人： Evangelos S. Eleftheriou ,  Robert Haas ,  Xiao-Yu Hu ,  Dung Nguyen

    发明人： Evangelos S. Eleftheriou ,  Robert Haas ,  Xiao-Yu Hu ,  Dung Nguyen

    IPC分类号： H03M13/11

    CPC分类号： H03M13/1105 ,  H03M13/1108 ,  H03M13/2957

    摘要： It is provided a method for decoding a sequence of bits encoded by a LPDC code. The method comprises providing a set of bit states, including a first state and a second state, and a set of conditions to change a bit state including a first condition 5 and a second condition. The first condition and the second condition are different. The method comprises reading the value of each bit of the sequence, associating each bit to a respective state of the set according to the values as read, determining that an evaluated condition is met and changing the state of the target bit as a result of the condition being met. The method may then set the value of the target bit of the 10 sequence according to the state thereof. Such a method provides a solution for decoding a sequence of bits encoded by a LDPC code with better performance than the classic bit-flipping algorithm with only a slight increase in complexity.

    摘要翻译： 提供了一种用于解码由LPDC码编码的比特序列的方法。 该方法包括提供一组位状态，包括第一状态和第二状态，以及一组条件以改变包括第一条件5和第二状态的位状态。 第一个条件和第二个条件是不同的。 该方法包括读取序列的每个比特的值，根据读取的值将每个比特与组的相应状态相关联，确定满足评估条件并改变目标比特的状态作为结果 条件得到满足 然后，该方法可以根据其状态设置10序列的目标比特的值。 这种方法提供了一种解码方案，用于以比典型的比特翻转算法更好的性能来解码由LDPC码编码的比特序列，只有稍微增加的复杂度。

    Cache memory management in a flash cache architecture
    27.
    发明授权
    Cache memory management in a flash cache architecture 失效
    缓存内存管理在闪存缓存架构中

    公开(公告)号：US08688897B2

    公开(公告)日：2014-04-01

    申请号：US13080655

    申请日：2011-04-05

    申请人： Evangelos S. Eleftheriou ,  Robert Haas ,  Xiao-Yu Hu ,  Roman A. Pletka

    发明人： Evangelos S. Eleftheriou ,  Robert Haas ,  Xiao-Yu Hu ,  Roman A. Pletka

    IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F9/26 ,  G06F9/34

    CPC分类号： G06F12/0246 ,  G06F12/0871 ,  G06F12/0897 ,  G06F2212/222 ,  G06F2212/7202

    摘要： Provided are a system, method, and computer program product for managing cache memory to cache data units in at least one storage device. A cache controller is coupled to at least two flash bricks, each comprising a flash memory. Metadata indicates a mapping of the data units to the flash bricks caching the data units, wherein the metadata is used to determine the flash bricks on which the cache controller caches received data units. The metadata is updated to indicate the flash brick having the flash memory on which data units are cached.

    摘要翻译： 提供了一种用于管理高速缓冲存储器以在至少一个存储设备中缓存数据单元的系统，方法和计算机程序产品。 高速缓存控制器耦合到至少两个闪存块，每个闪存块包括闪存。 元数据表示数据单元与缓存数据单元的闪存块的映射，其中元数据用于确定高速缓存控制器高速缓存接收的数据单元的闪存块。 更新元数据以指示闪存块具有缓存数据单元的闪存。

    Write-erase endurance lifetime of memory storage devices
    29.
    发明授权
    Write-erase endurance lifetime of memory storage devices 有权
    存储器存储设备的写擦除耐久寿命

    公开(公告)号：US08402242B2

    公开(公告)日：2013-03-19

    申请号：US12511577

    申请日：2009-07-29

    申请人： Xiao-yu Hu ,  Evangelos S. Eleftheriou ,  Robert Haas

    发明人： Xiao-yu Hu ,  Evangelos S. Eleftheriou ,  Robert Haas

    IPC分类号： G06F12/00

    CPC分类号： B62D35/001 ,  G06F12/0246 ,  G06F2212/1044 ,  G06F2212/7205 ,  G06F2212/7211 ,  G11C16/349 ,  G11C16/3495

    摘要： A memory management system and method for managing memory blocks of a memory device of a computer. The system includes a free block data structure including free memory blocks for writing, and sorting the free memory blocks in a predetermined order based on block write-erase endurance cycle count and receiving new user-write requests to update existing data and relocation write requests to relocate existing data separately, a user-write block pool for receiving youngest blocks holding user-write data (i.e., any page being updated frequently) from the free block data structure, a relocation block pool for receiving oldest blocks holding relocation data (i.e., any page being updated infrequently) from the free block data structure, and a garbage collection pool structure for selecting at least one of user-write blocks and relocation blocks for garbage collection, wherein the selected block is moved back to the free block data structure upon being relocated and erased.

    摘要翻译： 一种用于管理计算机的存储器件的存储器块的存储器管理系统和方法。 该系统包括一个空闲块数据结构，包括用于写入的空闲存储器块，并且基于块写擦除耐久循环计数以预定顺序对可用存储器块进行排序，并且接收新的用户写入请求以更新现有数据和重定位写请求 重新定位现有数据，用于从空闲块数据结构接收持有用户写入数据（即，任何频繁更新的页面）的最小块的用户写入块池，用于接收保存重定位数据的最旧块的重定位块池（即， 任何不经常更新的页面）以及用于选择用于垃圾回收的用户写入块和重定位块中的至少一个的垃圾收集池结构，其中所选择的块被移动回到空闲块数据结构 被搬迁和删除。

    Memory management in a non-volatile solid state memory device
    30.
    发明授权
    Memory management in a non-volatile solid state memory device 有权
    非易失性固态存储器件中的内存管理

    公开(公告)号：US08370712B2

    公开(公告)日：2013-02-05

    申请号：US12835783

    申请日：2010-07-14

    申请人： Evangelos S Eleftheriou ,  Ilias Iliadis ,  Robert Haas ,  Xiaoyu Hu

    发明人： Evangelos S Eleftheriou ,  Ilias Iliadis ,  Robert Haas ,  Xiaoyu Hu

    IPC分类号： G11C29/00 ,  G11C11/34

    CPC分类号： G06F11/1068 ,  G11C16/349 ,  G11C16/3495

    摘要： A computer-implemented method of managing a memory of a non-volatile solid state memory device by balancing write/erase cycles among blocks to level block usage. The method includes: monitoring an occurrence of an error during a read operation in a memory unit of the device, wherein the error is correctable by error-correcting code; and programming the memory unit according to the monitored occurrence of the error; wherein the step of monitoring the occurrence of an error is carried out for at least one block; and wherein said step of programming comprises wear-leveling the monitored block according the error monitored for the monitored block. A computer system and a computer program-product is also provided.The non-volatile solid state memory device includes: a memory unit having data stored therein; and a controller with a logic for programming the memory unit according to a monitored occurrence of an error during a read operation. The method includes: monitoring an occurrence of an error during a read operation in a memory unit of the device; and programming the memory unit according to the monitored occurrence of the error.

    摘要翻译： 一种计算机实现的通过平衡块之间的写入/擦除循环来平衡块使用来管理非易失性固态存储器件的存储器的方法。 该方法包括：在设备的存储器单元中的读取操作期间监视错误的发生，其中可通过纠错码校正错误; 并根据所监视的错误发生来对存储器单元进行编程; 其中，针对至少一个块执行监视错误发生的步骤; 并且其中所述编程步骤包括根据所监视的块监测的误差来磨损所监视的块。 还提供了计算机系统和计算机程序产品。 非易失性固态存储装置包括：具有存储在其中的数据的存储单元; 以及控制器，具有用于根据在读取操作期间监视的错误发生来对存储器单元进行编程的逻辑。 该方法包括：在设备的存储器单元中的读取操作期间监视错误的发生; 并根据监视出现的错误对存储器单元进行编程。