利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

53 条记录 (耗时 0.026 秒)

    DEEP TRENCH CAPACITOR
    21.
    发明申请
    DEEP TRENCH CAPACITOR 有权
    深层电容电容

    公开(公告)号：US20140070292A1

    公开(公告)日：2014-03-13

    申请号：US13606448

    申请日：2012-09-07

    申请人： Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

    发明人： Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

    IPC分类号： H01L27/108 ,  H01L21/311

    CPC分类号： H01L28/60 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/1203 ,  H01L29/66181

    摘要： A method of forming a deep trench capacitor in a semiconductor-on-insulator substrate is provided. The method may include providing a pad layer positioned above a bulk substrate, etching a deep trench into the pad layer and the bulk substrate extending from a top surface of the pad layer down to a location within the bulk substrate, and doping a portion of the bulk substrate to form a buried plate. The method further including depositing a node dielectric, an inner electrode, and a dielectric cap substantially filling the deep trench, the node dielectric being located between the buried plate and the inner electrode, the dielectric cap being located at a top of the deep trench, removing the pad layer, growing an insulator layer on top of the bulk substrate, and growing a semiconductor-on-insulator layer on top of the insulator layer.

    摘要翻译： 提供了在绝缘体上半导体衬底中形成深沟槽电容器的方法。 该方法可以包括提供定位在大块衬底之上的衬垫层，将深沟槽蚀刻到衬垫层中，以及从衬垫层的顶表面延伸到体衬底内的位置的本体衬底，以及掺杂 散装衬底形成掩埋板。 该方法还包括沉积基本上填充深沟槽的节点电介质，内部电极和电介质帽，节点电介质位于掩埋板和内部电极之间，电介质帽位于深沟槽的顶部， 去除衬垫层，在本体衬底的顶部上生长绝缘体层，以及在绝缘体层的顶部上生长绝缘体上半导体层。

    SPACER ISOLATION IN DEEP TRENCH
    22.
    发明申请
    SPACER ISOLATION IN DEEP TRENCH 有权
    深层隔离器中的间隔隔离

    公开(公告)号：US20130328157A1

    公开(公告)日：2013-12-12

    申请号：US13489572

    申请日：2012-06-06

    申请人： Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

    发明人： Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

    IPC分类号： H01L29/00 ,  H01L21/762

    CPC分类号： H01L29/0649 ,  H01L27/10829 ,  H01L27/10861 ,  H01L27/10867 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/945

    摘要： A method of forming improved spacer isolation in deep trench including recessing a node dielectric, a first conductive layer, and a second conductive layer each deposited within a deep trench formed in a silicon-on-insulator (SOI) substrate, to a level below a buried oxide layer of the SOI substrate, and creating an opening having a bottom surface in the deep trench. Further including depositing a spacer along a sidewall of the deep trench and the bottom surface of the opening, and removing the spacer from the bottom surface of the opening. Performing at least one of an ion implantation and an ion bombardment in one direction at an angle into an upper portion of the spacer. Removing the upper portion of the spacer from the sidewall of the deep trench. Depositing a third conductive layer within the opening.

    摘要翻译： 在深沟槽中形成改进的间隔隔离的方法，包括将形成在绝缘体上硅（SOI）衬底中的深沟槽内沉积的节点电介质，第一导电层和第二导电层凹入到低于 SOI衬底的掩埋氧化物层，并且在深沟槽中形成具有底表面的开口。 还包括沿深沟槽的侧壁和开口的底表面沉积间隔物，以及从开口的底表面移除隔离物。 在一个方向上以一定角度进行离子注入和离子轰击中的至少一个进入间隔物的上部。 从深沟槽的侧壁上去除隔离物的上部。 在开口内沉积第三导电层。

    Deep trench capacitor
    24.
    发明授权
    Deep trench capacitor 有权
    深沟槽电容器

    公开(公告)号：US09048339B2

    公开(公告)日：2015-06-02

    申请号：US13606448

    申请日：2012-09-07

    申请人： Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

    发明人： Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

    IPC分类号： H01L21/84 ,  H01L29/66 ,  H01L27/108 ,  H01L27/12

    CPC分类号： H01L28/60 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/1203 ,  H01L29/66181

    摘要： A method of forming a deep trench capacitor in a semiconductor-on-insulator substrate is provided. The method may include providing a pad layer positioned above a bulk substrate, etching a deep trench into the pad layer and the bulk substrate extending from a top surface of the pad layer down to a location within the bulk substrate, and doping a portion of the bulk substrate to form a buried plate. The method further including depositing a node dielectric, an inner electrode, and a dielectric cap substantially filling the deep trench, the node dielectric being located between the buried plate and the inner electrode, the dielectric cap being located at a top of the deep trench, removing the pad layer, growing an insulator layer on top of the bulk substrate, and growing a semiconductor-on-insulator layer on top of the insulator layer.

    摘要翻译： 提供了在绝缘体上半导体衬底中形成深沟槽电容器的方法。 该方法可以包括提供定位在大块衬底之上的衬垫层，将深沟槽蚀刻到衬垫层中，以及从衬垫层的顶表面延伸到体衬底内的位置的本体衬底，以及掺杂 散装衬底形成掩埋板。 该方法还包括沉积基本上填充深沟槽的节点电介质，内部电极和电介质帽，节点电介质位于掩埋板和内部电极之间，电介质帽位于深沟槽的顶部， 去除衬垫层，在本体衬底的顶部上生长绝缘体层，以及在绝缘体层的顶部上生长绝缘体上半导体层。

    SUBLITHOGRAPHIC WIDTH FINFET EMPLOYING SOLID PHASE EPITAXY
    25.
    发明申请
    SUBLITHOGRAPHIC WIDTH FINFET EMPLOYING SOLID PHASE EPITAXY 有权
    使用固体相外延片的子图形宽度FINFET

    公开(公告)号：US20140061793A1

    公开(公告)日：2014-03-06

    申请号：US13597752

    申请日：2012-08-29

    申请人： Chengwen Pei ,  Kangguo Cheng ,  Joseph Ervin ,  Juntao Li ,  Ravi M. Todi ,  Geng Wang

    发明人： Chengwen Pei ,  Kangguo Cheng ,  Joseph Ervin ,  Juntao Li ,  Ravi M. Todi ,  Geng Wang

    IPC分类号： H01L27/12 ,  H01L29/06 ,  H01L21/336

    CPC分类号： H01L27/0886 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/66795

    摘要： A dielectric mandrel structure is formed on a single crystalline semiconductor layer. An amorphous semiconductor material layer is deposited on the physically exposed surfaces of the single crystalline semiconductor layer and surfaces of the mandrel structure. Optionally, the amorphous semiconductor material layer can be implanted with at least one different semiconductor material. Solid phase epitaxy is performed on the amorphous semiconductor material layer employing the single crystalline semiconductor layer as a seed layer, thereby forming an epitaxial semiconductor material layer with uniform thickness. Remaining portions of the epitaxial semiconductor material layer are single crystalline semiconductor fins and thickness of these fins are sublithographic. After removal of the dielectric mandrel structure, the single crystalline semiconductor fins can be employed to form a semiconductor device.

    摘要翻译： 介电心轴结构形成在单晶半导体层上。 非晶半导体材料层沉积在单晶半导体层的物理暴露表面和心轴结构的表面上。 可选地，非晶半导体材料层可以注入至少一种不同的半导体材料。 在采用单晶半导体层作为种子层的非晶半导体材料层上进行固相外延，从而形成厚度均匀的外延半导体材料层。 外延半导体材料层的剩余部分是单晶半导体鳍片，并且这些鳍片的厚度是亚光刻的。 在去除介电心轴结构之后，可以采用单晶半导体鳍形成半导体器件。

    Recessed Single Crystalline Source and Drain For Semiconductor-On-Insulator Devices
    27.
    发明申请
    Recessed Single Crystalline Source and Drain For Semiconductor-On-Insulator Devices 有权
    嵌入式半导体绝缘体器件的单晶硅和漏极

    公开(公告)号：US20130105898A1

    公开(公告)日：2013-05-02

    申请号：US13285162

    申请日：2011-10-31

    申请人： Geng Wang ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi

    发明人： Geng Wang ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/66477 ,  H01L21/84 ,  H01L27/1203

    摘要： After formation of a gate stack, regions in which a source and a drain are to be formed are recessed through the top semiconductor layer and into an upper portion of a buried single crystalline rare earth oxide layer of a semiconductor-on-insulator (SOI) substrate so that a source trench and drain trench are formed. An embedded single crystalline semiconductor portion epitaxially aligned to the buried single crystalline rare earth oxide layer is formed in each of the source trench and the drain trench to form a recessed source and a recessed drain, respectively. Protrusion of the recessed source and recessed drain above the bottom surface of a gate dielectric can be minimized to reduce parasitic capacitive coupling with a gate electrode, while providing low source resistance and drain resistance through the increased thickness of the recessed source and recessed drain relative to the thickness of the top semiconductor layer.

    摘要翻译： 在形成栅极叠层之后，要形成源极和漏极的区域通过顶部半导体层凹陷，并进入绝缘体上半导体（SOI）的掩埋的单晶稀土氧化物层的上部， 衬底，从而形成源极沟槽和漏极沟槽。 在源极沟槽和漏极沟槽的每一个中分别形成外延对齐于埋入的单晶稀土氧化物层的嵌入式单晶半导体部分，以分别形成凹陷源和凹陷漏极。 可以将栅极电介质的底表面之上的凹陷源和凹陷漏极的突起最小化，以减少与栅极电极的寄生电容耦合，同时通过凹陷源和凹陷漏极的增加的厚度提供低的源极电阻和漏极电阻，相对于 顶部半导体层的厚度。

    Sublithographic width finFET employing solid phase epitaxy
    28.
    发明授权
    Sublithographic width finFET employing solid phase epitaxy 有权
    使用固相外延的亚光刻宽度finFET

    公开(公告)号：US09064745B2

    公开(公告)日：2015-06-23

    申请号：US13597752

    申请日：2012-08-29

    申请人： Chengwen Pei ,  Kangguo Cheng ,  Joseph Ervin ,  Juntao Li ,  Ravi M. Todi ,  Geng Wang

    发明人： Chengwen Pei ,  Kangguo Cheng ,  Joseph Ervin ,  Juntao Li ,  Ravi M. Todi ,  Geng Wang

    IPC分类号： H01L21/336 ,  H01L27/12 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/66 ,  H01L27/092

    CPC分类号： H01L27/0886 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/66795

    摘要： A dielectric mandrel structure is formed on a single crystalline semiconductor layer. An amorphous semiconductor material layer is deposited on the physically exposed surfaces of the single crystalline semiconductor layer and surfaces of the mandrel structure. Optionally, the amorphous semiconductor material layer can be implanted with at least one different semiconductor material. Solid phase epitaxy is performed on the amorphous semiconductor material layer employing the single crystalline semiconductor layer as a seed layer, thereby forming an epitaxial semiconductor material layer with uniform thickness. Remaining portions of the epitaxial semiconductor material layer are single crystalline semiconductor fins and thickness of these fins are sublithographic. After removal of the dielectric mandrel structure, the single crystalline semiconductor fins can be employed to form a semiconductor device.

    摘要翻译： 介电心轴结构形成在单晶半导体层上。 非晶半导体材料层沉积在单晶半导体层的物理暴露表面和心轴结构的表面上。 可选地，非晶半导体材料层可以注入至少一种不同的半导体材料。 在采用单晶半导体层作为种子层的非晶半导体材料层上进行固相外延，从而形成厚度均匀的外延半导体材料层。 外延半导体材料层的剩余部分是单晶半导体鳍片，并且这些鳍片的厚度是亚光刻的。 在去除介电心轴结构之后，可以采用单晶半导体鳍形成半导体器件。

    Multilayer MIM capacitor
    29.
    发明授权
    Multilayer MIM capacitor 有权
    多层MIM电容

    公开(公告)号：US08962423B2

    公开(公告)日：2015-02-24

    申请号：US13352655

    申请日：2012-01-18

    申请人： Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

    发明人： Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

    IPC分类号： H01L21/8242

    CPC分类号： H01L28/40 ,  H01L21/32134 ,  H01L28/86 ,  H01L28/90 ,  H01L28/91

    摘要： An improved semiconductor capacitor and method of fabrication is disclosed. A MIM stack, comprising alternating first-type and second-type metal layers (each separated by dielectric) is formed in a deep cavity. The entire stack can be planarized, and then patterned to expose a first area, and selectively etched to recess all first metal layers within the first area. A second selective etch is performed to recess all second metal layers within a second area. The etched recesses can be backfilled with dielectric. Separate electrodes can be formed; a first electrode formed in said first area and contacting all of said second-type metal layers and none of said first-type metal layers, and a second electrode formed in said second area and contacting all of said first-type metal layers and none of said second-type metal layers.

    摘要翻译： 公开了一种改进的半导体电容器和制造方法。 在深空腔中形成MIM叠层，其包括交替的第一和第二类型的金属层（各自被电介质隔开）。 整个堆叠可以被平坦化，然后被图案化以暴露第一区域，并且被选择性地蚀刻以在第一区域内凹陷所有第一金属层。 执行第二选择性蚀刻以在第二区域内凹陷所有第二金属层。 蚀刻的凹槽可以用电介质回填。 可以形成单独的电极; 第一电极，形成在所述第一区域中，并且与所有所述第二类型金属层和所述第一类型金属层接触，并且形成在所述第二区域中并与所有第一类金属层接触的第二电极， 所述第二类金属层。

    Rare-earth oxide isolated semiconductor fin
    30.
    发明授权
    Rare-earth oxide isolated semiconductor fin 有权
    稀土氧化物隔离半导体鳍片

    公开(公告)号：US08853781B2

    公开(公告)日：2014-10-07

    申请号：US13328358

    申请日：2011-12-16

    申请人： Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

    发明人： Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

    IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

    CPC分类号： H01L21/02488 ,  H01L21/02513 ,  H01L21/02587 ,  H01L21/02598 ,  H01L21/02642 ,  H01L29/66795 ,  H01L29/785

    摘要： A dielectric template layer is deposited on a substrate. Line trenches are formed within the dielectric template layer by an anisotropic etch that employs a patterned mask layer. The patterned mask layer can be a patterned photoresist layer, or a patterned hard mask layer that is formed by other image transfer methods. A lower portion of each line trench is filled with an epitaxial rare-earth oxide material by a selective rare-earth oxide epitaxy process. An upper portion of each line trench is filled with an epitaxial semiconductor material by a selective semiconductor epitaxy process. The dielectric template layer is recessed to form a dielectric material layer that provides lateral electrical isolation among fin structures, each of which includes a stack of a rare-earth oxide fin portion and a semiconductor fin portion.

    摘要翻译： 电介质模板层沉积在衬底上。 通过使用图案化掩模层的各向异性蚀刻，在电介质模板层内形成线沟槽。 图案化掩模层可以是图案化的光致抗蚀剂层，或者通过其它图像转印方法形成的图案化的硬掩模层。 通过选择性稀土氧化物外延法，用外延稀土氧化物材料填充每个线沟槽的下部。 通过选择性半导体外延工艺，用外延半导体材料填充每个线沟槽的上部。 电介质模板层被凹入以形成介电材料层，该电介质材料层在散热片结构之间提供横向电隔离，其中每一个包括稀土氧化物翅片部分和半导体散热片部分的堆叠。