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106 条记录 (耗时 0.035 秒)

    Writing to asymmetric memory
    21.
    发明授权
    Writing to asymmetric memory 有权
    写入不对称记忆

    公开(公告)号：US08266407B2

    公开(公告)日：2012-09-11

    申请号：US13053371

    申请日：2011-03-22

    申请人： Vijay Karamcheti ,  Kenneth A. Okin ,  Kumar Ganapathy ,  Ashish Singhai ,  Rajesh Parekh

    发明人： Vijay Karamcheti ,  Kenneth A. Okin ,  Kumar Ganapathy ,  Ashish Singhai ,  Rajesh Parekh

    IPC分类号： G06F12/00

    CPC分类号： G06F12/1009 ,  G06F3/0604 ,  G06F3/0628 ,  G06F3/0638 ,  G06F3/064 ,  G06F3/0646 ,  G06F3/0647 ,  G06F3/068 ,  G06F3/0685 ,  G06F9/5016 ,  G06F12/0207 ,  G06F12/0223 ,  G06F12/0292 ,  G06F12/08 ,  G06F12/10 ,  G06F12/121 ,  G06F12/1475 ,  G06F13/1657 ,  G06F13/1694 ,  G06F2212/205 ,  G06F2212/657 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/22

    摘要： A memory controller writes to a virtual address associated with data residing within an asymmetric memory component of main memory that is within a computer system and that has a symmetric memory component, while preserving proximate other data residing within the asymmetric memory component. The symmetric memory component within the main memory of the computer system is configured to enable random access write operations in which an address within a block of the symmetric memory component is written without affecting the availability of other addresses within the block of the symmetric memory component during the writing of that address. The asymmetric memory component is configured to enable block write operations in which writing to an address within a region of the asymmetric memory component affects the availability of other addresses within the region of the asymmetric memory component during the block write operations involving the address.

    摘要翻译： 存储器控制器写入与驻留在计算机系统内的主存储器的非对称存储器组件内的数据相关联的虚拟地址，并且具有对称存储器组件，同时保留驻留在非对称存储器组件内的邻近其他数据。 计算机系统的主存储器内的对称存储器组件被配置为实现随机存取写入操作，其中写入对称存储器组件的块内的地址而不影响对称存储器组件的块内的其他地址的可用性 写这个地址。 非对称存储器组件被配置为启用块写入操作，其中对非对称存储器组件的区域内的地址的写入在涉及地址的块写入操作期间影响非对称存储器组件的区域内的其他地址的可用性。

    METHODS FOR MAIN MEMORY WITH NON-VOLATILE TYPE MEMORY MODULES
    25.
    发明申请
    METHODS FOR MAIN MEMORY WITH NON-VOLATILE TYPE MEMORY MODULES 有权
    具有非易失型存储器模块的主存储器的方法

    公开(公告)号：US20100274959A1

    公开(公告)日：2010-10-28

    申请号：US12832409

    申请日：2010-07-08

    申请人： Vijay Karamcheti ,  Kumar Ganapathy ,  Kenneth Alan Okin ,  Rajesh Parekh

    发明人： Vijay Karamcheti ,  Kumar Ganapathy ,  Kenneth Alan Okin ,  Rajesh Parekh

    IPC分类号： G06F12/00 ,  G06F12/02 ,  G06F17/30

    CPC分类号： G06F13/4009 ,  G06F12/0638 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

    摘要： A computing system is disclosed that includes a memory controller in a processor socket normally reserved for a processor. A plurality of non-volatile memory modules may be plugged into memory sockets normally reserved for DRAM memory modules. The non-volatile memory modules may be accessed using a data communication protocol to access the non-volatile memory modules. The memory controller controls read and write accesses to the non-volatile memory modules. The memory sockets are coupled to the processor socket by printed circuit board traces. The data communication protocol to access the non-volatile memory modules is communicated over the printed circuit board traces and through the sockets normally used to access DRAM type memory modules.

    摘要翻译： 公开了一种计算系统，其包括通常为处理器预留的处理器插座中的存储器控​​制器。 多个非易失性存储器模块可以插入通常保留给DRAM存储器模块的存储器插槽中。 可以使用数据通信协议访问非易失性存储器模块以访问非易失性存储器模块。 存储器控制器控制对非易失性存储器模块的读取和写入访问。 存储器插座通过印刷电路板迹线耦合到处理器插座。 用于访问非易失性存储器模块的数据通信协议通过印刷电路板迹线和通常用于访问DRAM型存储器模块的插槽来传送。

    METHODS AND SYSTEMS FOR TWO-DIMENSIONAL MAIN MEMORY
    26.
    发明申请
    METHODS AND SYSTEMS FOR TWO-DIMENSIONAL MAIN MEMORY 有权
    二维主记忆的方法和系统

    公开(公告)号：US20090210636A1

    公开(公告)日：2009-08-20

    申请号：US12369728

    申请日：2009-02-11

    申请人： Vijay Karamcheti ,  Kumar Ganapathy

    发明人： Vijay Karamcheti ,  Kumar Ganapathy

    IPC分类号： G06F12/02

    CPC分类号： G06F12/0246 ,  G11C5/04 ,  G11C29/76

    摘要： In one embodiment of the invention, a memory module is disclosed including a printed circuit board with an edge connector; an address controller coupled to the printed circuit board; and a plurality of memory slices. Each of the plurality of memory slices of the memory module includes one or more memory integrated circuits coupled to the printed circuit board, and a slave memory controller coupled to the printed circuit board and the one or more memory integrated circuits. The slave memory controller receives memory access requests for the memory module from the address controller. The slave memory controller selectively activates one or more of the one or more memory integrated circuits in the respective memory slice in response to the address received from the address controller to read data from or write data into selected memory locations in the memory integrated circuits.

    摘要翻译： 在本发明的一个实施例中，公开了一种存储器模块，其包括具有边缘连接器的印刷电路板; 耦合到所述印刷电路板的地址控制器; 和多个存储器片。 存储器模块的多个存储器片段中的每一个包括耦合到印刷电路板的一个或多个存储器集成电路，以及耦合到印刷电路板和一个或多个存储器集成电路的从存储器控制器。 从存储器控制器从地址控制器接收存储器模块的存储器访问请求。 从存储器控制器响应于从地址控制器接收到的地址来选择性地激活相应存储器片中的一个或多个存储器集成电路中的一个或多个，以将数据从存储器集成电路中的选择的存储器位置读取或写入数据。

    Dyadic instruction processing instruction set architecture with 20-bit and 40-bit DSP and control instructions
    28.
    发明授权
    Dyadic instruction processing instruction set architecture with 20-bit and 40-bit DSP and control instructions 失效
    具有20位和40位DSP的二进制指令处理指令集架构和控制指令

    公开(公告)号：US06772319B2

    公开(公告)日：2004-08-03

    申请号：US10215721

    申请日：2002-08-08

    申请人： Kumar Ganapathy ,  Ruban Kanapathipillai

    发明人： Kumar Ganapathy ,  Ruban Kanapathipillai

    IPC分类号： G06F9302

    CPC分类号： G06F9/3877 ,  G06F9/3001 ,  G06F9/30072 ,  G06F9/30149 ,  G06F9/30189 ,  G06F9/381 ,  G06F9/382 ,  G06F9/3853 ,  G06F9/3885 ,  G06F15/8015

    摘要： An instruction set architecture (ISA) to convert voice and data samples into packets for transmission over a network and to convert packets received from the network into voice and data samples. In one embodiment, the ISA includes a digital signal processing (DSP) instruction set architecture for a plurality of signal processing units and a control instruction set architecture to control the execution of DSP instructions by the plurality of signal processing units. In another embodiment, the ISA includes a plurality of DSP instructions including a 20-bit DSP instruction and a 40-bit DSP instruction and a plurality of control instructions to control execution of the plurality of DSP instructions including a 20-bit control instruction and a 40-bit control instruction. The DSP instructions may be dyadic DSP instructions including a main DSP operation and a sub DSP operation.

    摘要翻译： 一种指令集架构（ISA），用于将语音和数据样本转换成分组，用于通过网络进行传输，并将从网络接收的数据包转换为语音和数据样本。 在一个实施例中，ISA包括用于多个信号处理单元的数字信号处理（DSP）指令集架构和用于控制由多个信号处理单元执行DSP指令的控制指令集架构。 在另一个实施例中，ISA包括多个DSP指令，包括20位DSP指令和40位DSP指令以及多个控制指令，以控制多个DSP指令的执行，包括20位控制指令和 40位控制指令。 DSP指令可以是二进制DSP指令，包括主DSP操作和子DSP操作。

    Dyadic DSP instructions for digital signal processors
    29.
    发明授权
    Dyadic DSP instructions for digital signal processors 失效

    公开(公告)号：US06631461B2

    公开(公告)日：2003-10-07

    申请号：US10216575

    申请日：2002-08-08

    申请人： Kumar Ganapathy ,  Ruban Kanapathipillai

    发明人： Kumar Ganapathy ,  Ruban Kanapathipillai

    IPC分类号： G06F9302

    CPC分类号： G06F9/3877 ,  G06F9/3001 ,  G06F9/30072 ,  G06F9/30149 ,  G06F9/30189 ,  G06F9/381 ,  G06F9/382 ,  G06F9/3853 ,  G06F9/3885 ,  G06F15/8015

    摘要： An instruction set architecture (ISA) for application specific signal processor (ASSP) is tailored to digital signal processing applications. The instruction set architecture implemented with the ASSP, is adapted to DSP algorithmic structures. The instruction word of the ISA is typically 20 bits but can be expanded to 40-bits to control two instructions to be executed in series or parallel. All DSP instructions of the ISA are dyadic DSP instructions performing two operations with one instruction in one cycle. The DSP instructions or operations in the preferred embodiment include a multiply instruction (MULT), an addition instruction (ADD), a minimize/maximize instruction (MIN/MAX) also referred to as an extrema instruction, and a no operation instruction (NOP) each having an associated operation code (“opcode”). The present invention efficiently executes DSP instructions by means of the instruction set architecture and the hardware architecture of the application specific signal processor.

    Multi-chip packaged integrated circuit with flash memory and slave memory controller
    30.
    发明授权
    Multi-chip packaged integrated circuit with flash memory and slave memory controller 有权
    具有闪存和从属存储器控制器的多芯片封装集成电路

    公开(公告)号：US09093150B2

    公开(公告)日：2015-07-28

    申请号：US14016224

    申请日：2013-09-03

    申请人： Vijay Karamcheti ,  Kumar Ganapathy

    发明人： Vijay Karamcheti ,  Kumar Ganapathy

    IPC分类号： G11C16/04 ,  G06F12/06 ,  G06F17/30 ,  G06F12/02

    CPC分类号： G11C16/0408 ,  G06F7/78 ,  G06F12/0207 ,  G06F12/0246 ,  G06F12/0607 ,  G06F17/30477 ,  G06F2212/7201 ,  G06F2212/7208 ,  G11C16/06 ,  Y02D10/13

    摘要： A multi-chip packaged integrated circuit part for mounting to a printed circuit board of a memory module. The multi-chip packaged integrated circuit part comprises an integrated circuit package including a slave memory controller (SMC) die; and pairs of a spacer under the slave memory controller die, and a flash memory die under the spacer. In each pair, the flash memory die may be larger than the spacer so that an opening is provided into a perimeter of the flash memory die to allow electrical connections to be made. A plurality of conductors may be used to electrically couple the slave memory controller die and the flash memory die to one or more pads of a pin-out of the integrated circuit package.

    摘要翻译： 一种用于安装到存储器模块的印刷电路板的多芯片封装集成电路部件。 多芯片封装集成电路部分包括集成电路封装，其包括从存储器控制器（SMC）管芯; 以及在从存储器控制器管芯之下的间隔物对，以及在间隔件下的闪存管芯。 在每对中，闪存芯片可以大于间隔件，使得开口设置在闪存芯片的周边中，以允许进行电连接。 可以使用多个导体来将从存储器控制器管芯和闪存管芯电耦合到集成电路封装的引脚输出的一个或多个焊盘。