公开(公告)号：US20090015310A1

公开(公告)日：2009-01-15

申请号：US12208847

申请日：2008-09-11

申请人： Tomohisa TAKAI ,  Ryo Fukuda

发明人： Tomohisa TAKAI ,  Ryo Fukuda

IPC分类号： H03K3/00

CPC分类号： G11C29/028 ,  G11C7/20 ,  G11C16/20 ,  G11C29/802 ,  G11C2029/4402

摘要： A semiconductor device transfers first data to a circuit block. The semiconductor device is provided with a storage circuit configured to store the first data, a shift register configured to set the first data, a transfer circuit configured to transfer the first data from the shift register to the circuit block, a first input terminal configured to receive a first signal indicating the end of a transfer operation, a resetting signal-generating circuit configured to generate a resetting signal for resetting the shift register based on the first signal, a setting signal-generating circuit configured to generate a setting signal for setting the first data in the shift register again after the shift register is reset, and an output circuit configured to externally output the first data that has been set again.

摘要翻译： 半导体器件将第一数据传送到电路块。 所述半导体装置具备：存储电路，被配置为存储所述第一数据，移位寄存器，被配置为设置所述第一数据;传送电路，被配置为将所述第一数据从所述移位寄存器传送到所述电路块;第一输入端， 接收指示传送操作结束的第一信号;复位信号发生电路，被配置为基于所述第一信号产生用于复位所述移位寄存器的复位信号;设置信号发生电路，被配置为产生用于设置所述移位寄存器的设置信号， 在移位寄存器复位之后，移位寄存器中的第一数据再次被配置为从外部输出再次被设置的第一数据。

公开(公告)号：US07433978B2

公开(公告)日：2008-10-07

申请号：US11066250

申请日：2005-02-28

申请人： Tomohisa Takai ,  Ryo Fukuda

发明人： Tomohisa Takai ,  Ryo Fukuda

IPC分类号： G06F3/00

CPC分类号： G11C29/028 ,  G11C7/20 ,  G11C16/20 ,  G11C29/802 ,  G11C2029/4402

摘要： A semiconductor device transfers first data to a circuit block. The semiconductor device is provided with a storage circuit configured to store the first data, a shift register configured to set the first data, a transfer circuit configured to transfer the first data from the shift register to the circuit block, a first input terminal configured to receive a first signal indicating the end of a transfer operation, a resetting signal-generating circuit configured to generate a resetting signal for resetting the shift register based on the first signal, a setting signal-generating circuit configured to generate a setting signal for setting the first data in the shift register again after the shift register is reset, and an output circuit configured to externally output the first data that has been set again.

摘要翻译： 半导体器件将第一数据传送到电路块。 所述半导体装置具备：存储电路，被配置为存储所述第一数据，移位寄存器，被配置为设置所述第一数据;传送电路，被配置为将所述第一数据从所述移位寄存器传送到所述电路块;第一输入端， 接收指示传送操作结束的第一信号;复位信号发生电路，被配置为基于所述第一信号产生用于复位所述移位寄存器的复位信号;设置信号发生电路，被配置为产生用于设置所述移位寄存器的设置信号， 在移位寄存器复位之后，移位寄存器中的第一数据再次被配置为从外部输出再次被设置的第一数据。

公开(公告)号：US20080130358A1

公开(公告)日：2008-06-05

申请号：US11950097

申请日：2007-12-04

申请人： Ryo Fukuda

发明人： Ryo Fukuda

IPC分类号： G11C7/00

CPC分类号： G11C11/404 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2207/005 ,  G11C2207/2281 ,  G11C2211/4016

摘要： According to the semiconductor memory device of the embodiment, in the sense amplifier for the FBC, a first node and a second node can be disconnected from each other by a first isolation transistor. A third node and a fourth node can be disconnected from each other by a second isolation transistor. The first node is connected to the first memory cell. The third node is connected to the second memory cell. A first amplification transistor and a second amplification transistor are connected between the first node and the third node. A third amplification transistor and a fourth amplification transistor are connected between the second node and the fourth node. This enables to parallelly execute read data transfer to the data lines and precharge to prepare for the next read operation.

摘要翻译： 根据本实施例的半导体存储器件，在用于FBC的读出放大器中，第一节点和第二节点可以通过第一隔离晶体管彼此断开。 第三节点和第四节点可以通过第二隔离晶体管彼此断开。 第一个节点连接到第一个存储单元。 第三节点连接到第二个存储单元。 第一放大晶体管和第二放大晶体管连接在第一节点和第三节点之间。 第三放大晶体管和第四放大晶体管连接在第二节点和第四节点之间。 这使得能够并行地执行对数据线的读取数据传输并预充电以准备下一次读取操作。

公开(公告)号：US20070278580A1

公开(公告)日：2007-12-06

申请号：US11756196

申请日：2007-05-31

申请人： Masaki KONDO ,  Ryo Fukuda ,  Yohji Watanabe ,  Mitsutoshi Nakamura

发明人： Masaki KONDO ,  Ryo Fukuda ,  Yohji Watanabe ,  Mitsutoshi Nakamura

IPC分类号： H01L23/62 ,  H02H3/20

CPC分类号： H01L27/0251 ,  H01L23/62 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit device according to an embodiment of the present invention includes: a semiconductor substrate; an internal circuit formed on the semiconductor substrate, a first potential and a second potential being supplied to the internal circuit, thereby applying an operating voltage to the internal circuit; a fuse disposed above a semiconductor region of a first conductivity type, and electrically connected to the internal circuit, the semiconductor region being supplied with the second potential and being formed in the semiconductor substrate; and a protective element formed in the semiconductor region of the first conductivity type and protecting the internal circuit in response to positive and negative abnormal voltages generated in a wiring through which the fuse and the internal circuit are connected to each other.

摘要翻译： 根据本发明实施例的半导体集成电路器件包括：半导体衬底; 形成在所述半导体衬底上的内部电路，向所述内部电路供给第一电位和第二电位，从而向所述内部电路施加工作电压; 保险丝，其设置在第一导电类型的半导体区域上方，并且电连接到所述内部电路，所述半导体区域被提供有所述第二电位并形成在所述半导体衬底中; 以及形成在第一导电类型的半导体区域中的保护元件，并且响应于在熔丝和内部电路彼此连接的布线中产生的正和负异常电压来保护内部电路。

公开(公告)号：US07218560B2

公开(公告)日：2007-05-15

申请号：US11293378

申请日：2005-12-05

申请人： Ryo Fukuda ,  Yohji Watanabe ,  Shuso Fujii

发明人： Ryo Fukuda ,  Yohji Watanabe ,  Shuso Fujii

IPC分类号： G11C7/00

CPC分类号： H01L23/5258 ,  G11C17/16 ,  G11C17/18 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device includes a fuse element including a first terminal and a second terminal, which stores data based on whether or not it is electrically blown by a laser beam, a resistance element connected to the first terminal, a node in which the data is transferred, and a transistor provided between the resistance element and the node, which sets the data to the node.

摘要翻译： 一种半导体存储器件，包括：熔丝元件，包括第一端子和第二端子，该第一端子和第二端子基于其是否被激光束电熔接的数据，连接到第一端子的电阻元件，数据为 并且设置在电阻元件和节点之间的晶体管，其将数据设置到节点。

公开(公告)号：US20060114052A1

公开(公告)日：2006-06-01

申请号：US11272872

申请日：2005-11-15

申请人： Ryo Fukuda

发明人： Ryo Fukuda

IPC分类号： H01H37/76

CPC分类号： H01L23/5256 ,  G11C17/14 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is here disclosed a semiconductor integrated circuit comprising a laser beam irradiation object having one end portion at which a first potential is applied, a first transistor has a source and a drain wherein one of the source and the drain to which the other end portion of the object is electrically connected, a second transistor has a source and a drain wherein one of the source and the drain of the first transistor to which the other end portion is not electrically connected is electrically connected, and a storage circuit which is electrically connected to the one of the source and the drain of the second transistor to which the first transistor is electrically connected, and which is additionally electrically connected to the one of the source and the drain of the first transistor to which the other end portion is not electrically connected.

摘要翻译： 这里公开了一种半导体集成电路，包括：激光束照射对象，其具有施加第一电位的一个端部，第一晶体管具有源极和漏极，源极和漏极中的一个源极和漏极的另一个端部 物体电连接，第二晶体管具有源极和漏极，其中第一晶体管的源极和漏极之间的另一个端部未电连接的源极和漏极被电连接，并且存储电路电连接到 第一晶体管电连接的第二晶体管的源极和漏极之一，并且另外电连接到第一晶体管的源极和漏极之一，另一个端部未与其电连接 。

公开(公告)号：US06847564B2

公开(公告)日：2005-01-25

申请号：US10456478

申请日：2003-06-09

申请人： Ryo Fukuda

发明人： Ryo Fukuda

IPC分类号： G11C29/04 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4096 ,  G11C29/00 ,  G11C7/00 ,  G06F12/00

CPC分类号： G11C29/848 ,  G11C11/4096 ,  G11C2207/002

摘要： A semiconductor memory device includes a data line shift circuit, a plurality of data mask lines connected to the plurality of sense amplifier write circuits, respectively, and a plurality of mask circuits. The plurality of mask circuits each include at least one shift switch circuit and supply a mask signal to a sense amplifier write circuit, which is connected to a mask circuit different from that before a data line is shifted by the data line shift circuit, through the shift switch circuit and supply the mask signal to a sense amplifier write circuit, which is connected to the same mask circuit as that before the data line is shifted, not through the shift switch circuit.

公开(公告)号：US06601199B1

公开(公告)日：2003-07-29

申请号：US09405128

申请日：1999-09-24

申请人： Ryo Fukuda ,  Hironori Banba ,  Toshimasa Namekawa ,  Shinji Miyano

发明人： Ryo Fukuda ,  Hironori Banba ,  Toshimasa Namekawa ,  Shinji Miyano

IPC分类号： G01R3128

CPC分类号： G01R31/3167 ,  G01R31/318505 ,  Y10S257/909

摘要： A plurality of memory macros are laid out in a semiconductor chip. Macro ID generation circuits generate macro IDs for identifying the memory macros, and have different layouts. These macro ID generation circuits are arranged outside the memory macros in the semiconductor chip, so that test control blocks in the memory macros can use the same layouts between all the memory macros to reduce the design load.

摘要翻译： 多个存储器宏布置在半导体芯片中。 宏ID生成电路生成用于识别存储宏的宏ID，并具有不同的布局。 这些宏ID生成电路被布置在半导体芯片中的存储器宏之外，使得存储器宏中的测试控制块可以在所有存储器宏之间使用相同的布局来减少设计负载。

公开(公告)号：US08072830B2

公开(公告)日：2011-12-06

申请号：US12437123

申请日：2009-05-07

申请人： Ryo Fukuda

发明人： Ryo Fukuda

IPC分类号： G11C29/08

CPC分类号： G11C7/1006 ,  G11C7/1012 ,  G11C7/1051 ,  G11C2207/104 ,  G11C2207/105

摘要： A semiconductor integrated circuit device includes a plurality of memory macros, macro-common register block, and memory macro operation setting circuits. The macro-common register block has macro-common registers which are provided outside the plurality of memory macros and supply memory macro operation specifying signals to the plurality of memory macros. The memory macro operation setting circuits are respectively provided in the plurality of memory macros and are each configured to set an operating state of the memory macro in response to the memory macro operation specifying signal supplied from the macro-common register.

摘要翻译： 半导体集成电路器件包括多个存储器宏，宏公共寄存器块和存储器宏操作设置电路。 宏公共寄存器块具有宏公共寄存器，其设置在多个存储器宏之外，并且向多个存储器宏提供存储器宏操作指定信号。 存储器宏操作设置电路分别设置在多个存储器宏中，并且分别被配置为响应于从宏公共寄存器提供的存储器宏操作指定信号来设置存储器宏的操作状态。

公开(公告)号：US20110148211A1

公开(公告)日：2011-06-23

申请号：US12885935

申请日：2010-09-20

申请人： Fumiyoshi MATSUOKA ,  Ryo Fukuda

发明人： Fumiyoshi MATSUOKA ,  Ryo Fukuda

IPC分类号： H02J4/00

CPC分类号： H02M3/157 ,  Y10T307/696

摘要： In a semiconductor device according to the embodiment, a core circuit is an IC. A peripheral circuit includes a driver supplied with voltages from an internal power source and an external power source and outputting data transferred from the core circuit, and a fetch portion transferring the digital data to the driver. A first power source supplies an internal voltage to the driver via a power source line. A second power source includes current driving strings each including a current driving element and a switching element connected in series between the external power source and the power source line. The second power source supplies a current to the power source line separately from the first power source line by driving the current driving strings. A power source controller controls the second power source to drive the current driving strings when a logic transition occurs among consecutive bits of the data.

摘要翻译： 在根据实施例的半导体器件中，核心电路是IC。 外围电路包括从内部电源和外部电源提供电压的驱动器，并输出从核心电路传送的数据，以及将数字数据传送给驱动器的取出部分。 第一电源通过电源线向驱动器提供内部电压。 第二电源包括各自包括串联连接在外部电源和电源线之间的电流驱动元件和开关元件的电流驱动串。 第二电源通过驱动当前驱动串来将电流与第一电源线分开地提供给电源线。 当在数据的连续位之间发生逻辑转换时，电源控制器控制第二电源来驱动当前驱动串。