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    Adaptive matrix multiplication accelerator for machine learning and deep learning applications
    23.
    发明授权
    Adaptive matrix multiplication accelerator for machine learning and deep learning applications 有权

    公开(公告)号：US12153646B2

    公开(公告)日：2024-11-26

    申请号：US17967733

    申请日：2022-10-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongyan Jiang ,  Dimin Niu ,  Hongzhong Zheng

    IPC: G06F17/16 ,  G06F9/38 ,  G06F9/50

    Abstract: An adaptive matrix multiplier. In some embodiments, the matrix multiplier includes a first multiplying unit a second multiplying unit, a memory load circuit, and an outer buffer circuit. The first multiplying unit includes a first inner buffer circuit and a second inner buffer circuit, and the second multiplying unit includes a first inner buffer circuit and a second inner buffer circuit. The memory load circuit is configured to load data from memory, in a single burst of a burst memory access mode, into the first inner buffer circuit of the first multiplying unit; and into the first inner buffer circuit of the second multiplying unit.

    Adaptive matrix multiplication accelerator for machine learning and deep learning applications
    24.
    发明授权
    Adaptive matrix multiplication accelerator for machine learning and deep learning applications 有权

    公开(公告)号：US12141227B2

    公开(公告)日：2024-11-12

    申请号：US16942570

    申请日：2020-07-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongyan Jiang ,  Dimin Niu ,  Hongzhong Zheng

    IPC: G06F17/16 ,  G06F9/38 ,  G06F9/50

    Abstract: An adaptive matrix multiplier. In some embodiments, the matrix multiplier includes a first multiplying unit a second multiplying unit, a memory load circuit, and an outer buffer circuit. The first multiplying unit includes a first inner buffer circuit and a second inner buffer circuit, and the second multiplying unit includes a first inner buffer circuit and a second inner buffer circuit. The memory load circuit is configured to load data from memory, in a single burst of a burst memory access mode, into the first inner buffer circuit of the first multiplying unit; and into the first inner buffer circuit of the second multiplying unit.

    Multi-cell structure for non-volatile resistive memory
    27.
    发明授权
    Multi-cell structure for non-volatile resistive memory 有权

    公开(公告)号：US10929026B2

    公开(公告)日：2021-02-23

    申请号：US15136872

    申请日：2016-04-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dimin Niu ,  Mu-Tien Chang ,  Hongzhong Zheng

    IPC: G06F12/1009 ,  G06F12/02 ,  G06F3/06 ,  G11C13/00 ,  G11C8/06

    Abstract: A non-volatile memory comprises an array of a plurality of non-volatile memory cells, a controller coupled to the array, and an evaluator coupled to an output of the array. In a first operational mode, the controller receives a logical address and selects one non-volatile memory cell for access. In a second operational mode, and the controller receives a logical address and selects N non-volatile memory cells for access in which N is an integer greater than 1. If the logical address is for a read access, in the first operational mode the evaluator is disabled and the read-address output of the array corresponds to one selected non-volatile memory cell, and in the second operational mode the evaluator determines an read-address output corresponding to the received logical address based on a read output of the N selected non-volatile memory cells.

    Refresh aware replacement policy for volatile memory cache
    29.
    发明授权
    Refresh aware replacement policy for volatile memory cache 有权

    公开(公告)号：US10394719B2

    公开(公告)日：2019-08-27

    申请号：US15457813

    申请日：2017-03-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng

    IPC: G06F12/126 ,  G06F12/128 ,  G11C11/406

    Abstract: A method for replacing data on a volatile memory cache is provided. The volatile memory cache includes one or more memory banks and each of the memory banks includes a plurality of memory lines. The method includes: identifying a replacement ID for at least one of the memory lines to be replaced; identifying a refresh bank ID for one of the memory banks to be refreshed; determining whether or not a conflict exists between the replacement ID and the refresh bank ID; and selecting a new replacement ID if the conflict exists.

    DRAM ASSIST ERROR CORRECTION MECHANISM FOR DDR SDRAM INTERFACE
    30.
    发明申请
    DRAM ASSIST ERROR CORRECTION MECHANISM FOR DDR SDRAM INTERFACE 审中-公开

    公开(公告)号：US20190179704A1

    公开(公告)日：2019-06-13

    申请号：US16276304

    申请日：2019-02-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dimin Niu ,  Mu-Tien Chang ,  Hongzhong Zheng ,  Hyun-Joong Kim ,  Won-hyung Song ,  Jangseok Choi

    IPC: G06F11/10 ,  G11C29/42 ,  G11C29/52 ,  G11C5/04

    Abstract: A method of correcting a memory error of a dynamic random-access memory module (DRAM) using a double data rate (DDR) interface, the method includes conducting a memory transaction including multiple bursts with a memory controller to send data from data chips of the DRAM to the memory controller, detecting one or more errors using an ECC chip of the DRAM, determining a number of the bursts having the errors using the ECC chip of the DRAM, determining whether the number of the bursts having the errors is greater than a threshold number, determining a type of the errors, and directing the memory controller based on the determined type of the errors, wherein the DRAM includes a single ECC chip per memory channel.

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