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    INTERLEAVED PROGRAM AND VERIFY IN NON-VOLATILE MEMORY
    22.
    发明申请
    INTERLEAVED PROGRAM AND VERIFY IN NON-VOLATILE MEMORY 审中-公开

    公开(公告)号：US20200227124A1

    公开(公告)日：2020-07-16

    申请号：US16828477

    申请日：2020-03-24

    Applicant: SanDisk Technologies LLC

    Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Deepanshu Dutta

    IPC: G11C16/34 ,  G11C16/10

    Abstract: A circuit includes a program controller configured to perform a program operation with interleaved program-verify loops to program memory cells in a same block. During each program-verify loop, a control gate line voltage supply circuit first supplies a program pulse to a first cell of the block and then, before verifying the first cell, supplies a program pulse to a second cell of the block. After the program pulses are sent, the control gate line supply circuit consecutively supplies verify pulses to the first cell and the second cell such that a delay is introduced between the respective program and verify stages of the first and second cells. Additionally, a constant voltage bias on common control gate lines of the first and second memory cells is applied during the consecutive verify stages. Further, an order of verify pulses may be applied in a reverse order during a verify stage.

    NON-VOLATILE MEMORY WITH COUNTERMEASURE FOR SELECT GATE DISTURB
    23.
    发明申请
    NON-VOLATILE MEMORY WITH COUNTERMEASURE FOR SELECT GATE DISTURB 审中-公开

    公开(公告)号：US20200035312A1

    公开(公告)日：2020-01-30

    申请号：US16047599

    申请日：2018-07-27

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Dengtao Zhao ,  Deepanshu Dutta

    IPC: G11C16/34 ,  G11C16/10 ,  G11C16/08 ,  G11C16/04 ,  H01L27/11582

    Abstract: Program disturb is a condition that includes the unintended programming while performing a programming process for other memory cells. Such unintended programming can cause an error in the data being stored. In some cases, program disturb can result from electrons trapped in the channel being accelerated from one side of a dummy word line to another side of the dummy word line and redirected into a select gate. To prevent such program disturb, it is proposed to open the channel from one side of the dummy word line to the other side of the dummy word line after a sensing operation for program verify and prior to a subsequent programming voltage being applied. For example, the channel can be opened up by applying a voltage to the dummy word line prior to pre-charging unselected memory cells.

    Fast detection of defective memory block to prevent neighbor plane disturb
    25.
    发明授权
    Fast detection of defective memory block to prevent neighbor plane disturb 有权

    公开(公告)号：US10529435B2

    公开(公告)日：2020-01-07

    申请号：US15863404

    申请日：2018-01-05

    Applicant: SanDisk Technologies LLC

    Inventor： Sarath Puthenthermadam ,  Deepanshu Dutta ,  Long Pham

    IPC: G11C16/34 ,  G11C16/10 ,  G11C16/32 ,  G11C16/04

    Abstract: A bad block of memory cells is quickly detected and removed from further programming during concurrent multi-block program operations, to minimize a threshold voltage upshift in a good block. A difference in program speeds between the blocks can be quickly detected by detecting when the memory cells in each block pass a verify test, such as a verify test of a lowest programmed data state. If a first block passes the verify test at a reference program loop, a determination is made as to whether a second block passes the verify test within a specified number of additional program loops. If the second block meets this criterion, the program operation can continue for both blocks. However, if the second block does not meet this criterion, the program operation is terminated for the second block by isolating it from subsequent program and verify signals.

    SUBGROUP SELECTION FOR VERIFICATION
    26.
    发明申请
    SUBGROUP SELECTION FOR VERIFICATION 审中-公开

    公开(公告)号：US20190378583A1

    公开(公告)日：2019-12-12

    申请号：US16205165

    申请日：2018-11-29

    Applicant: SanDisk Technologies LLC

    Inventor： Yu-Chung Lien ,  Xiang Yang ,  Zhenming Zhou ,  Deepanshu Dutta ,  Huai-Yuan Tseng

    IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/32

    Abstract: An apparatus, system, and method are disclosed for identifying and selecting a subgroup of memory cells for use during a programming or erasing operation, in order to execute the programming or erasing operation in less time, while avoiding over and under programming errors. Memory devices disclosed herein may include a state change/programming circuit, a counting circuit, a determination circuit, an identification circuit, and/or a subgroup selection circuit, where each of these circuits are configured to perform operations related to the overall process of identifying and selecting the subgroup of memory cells for utilization during a programming operation.

    Dynamic anneal characteristics for annealing non-volatile memory
    27.
    发明授权
    Dynamic anneal characteristics for annealing non-volatile memory 有权

    公开(公告)号：US10467134B2

    公开(公告)日：2019-11-05

    申请号：US15247910

    申请日：2016-08-25

    Applicant: SanDisk Technologies LLC

    Inventor： Navneeth Kankani ,  Linh Truong ,  Sarath Puthenthermadam ,  Deepanshu Dutta

    IPC: G06F12/02

    Abstract: Apparatuses, systems, methods, and computer program products are disclosed for annealing non-volatile memory. A controller identifies one or more life cycle characteristics of a non-volatile storage element. The controller selects an anneal duration and an anneal temperature for annealing the non-volatile storage element. The anneal duration and the anneal temperature are based on the one or more life cycle characteristics. The controller anneals the non-volatile storage element using the selected anneal duration and anneal temperature.

    LOCKOUT NOISE REDUCTION CIRCUIT FOR STORAGE DEVICES
    28.
    发明申请
    LOCKOUT NOISE REDUCTION CIRCUIT FOR STORAGE DEVICES 审中-公开

    公开(公告)号：US20190267096A1

    公开(公告)日：2019-08-29

    申请号：US15908239

    申请日：2018-02-28

    Applicant: SanDisk Technologies LLC

    Inventor： Xiang Yang ,  Stanley Jeong ,  Wei Zhao ,  Huai-yuan Tseng ,  Deepanshu Dutta

    IPC: G11C16/24 ,  G11C16/26 ,  G11C16/34 ,  G11C7/08

    Abstract: A circuit includes selected sense circuits configured to be connected to selected bit lines and unselected sense circuits configured to be connected to unselected bit lines during a sense operation. When the sense circuit is connected to the unselected bit line during the sense operation, the sense circuit is locked out in order to reduce current consumption. However, noise from the locked out sense circuit may be transmitted to the sense circuits connected to the selected bit lines through adjacent bit line coupling. In order to reduce the effect of the noise, charge transfer from the sense node may be blocked from passing to the unselected bit lines. Or, charge may be drained from the sense node, thereby preventing the charge from passing to the unselected bit lines.

    Multi-die programming with die-jumping induced periodic delays
    29.
    发明授权
    Multi-die programming with die-jumping induced periodic delays 有权

    公开(公告)号：US10026492B2

    公开(公告)日：2018-07-17

    申请号：US15640563

    申请日：2017-07-02

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Deepanshu Dutta ,  Arash Hazeghi ,  Huai-Yuan Tseng ,  Cynthia Hsu ,  Navneeth Kankani

    IPC: G11C16/34 ,  G11C16/04 ,  G11C16/32

    Abstract: Systems and methods for improving the reliability of data stored in memory cells are described. To mitigate the effects of trapped electrons after one or more programming pulses have been applied to memory cells, a delay between the one or more programming pulses and subsequent program verify pulses may be set based on a chip temperature, the number of the one or more programming pulses that were applied to the memory cells, and/or the programming voltage that was applied to the memory cells during the one or more programming pulses. To mitigate the effects of residual electrons after one or more program verify pulses have been applied to memory cells, a delay between the one or more program verify pulses and subsequent programming pulses may be set based on a chip temperature and/or the programming voltage to be applied to the memory cells during the subsequent programming pulses.

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