公开(公告)号：US11276708B2

公开(公告)日：2022-03-15

申请号：US16891843

申请日：2020-06-03

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Akio Nishida ,  Mitsuteru Mushiga

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L25/18 ,  H01L21/768 ,  H01L27/11573 ,  H01L21/28 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556

Abstract: A memory die including a three-dimensional array of memory elements and a logic die including a peripheral circuitry that support operation of the three-dimensional array of memory elements can be bonded by die-to-die bonding to provide a bonded assembly. External bonding pads for the bonded assembly can be provided by forming recess regions through the memory die or through the logic die to physically expose metal interconnect structures within interconnect-level dielectric layers. The external bonding pads can include, or can be formed upon, a physically exposed subset of the metal interconnect structures. Alternatively or additionally, laterally-insulated external connection via structures can be formed through the bonded assembly to multiple levels of the metal interconnect structures. Further, through-dielectric external connection via structures extending through a stepped dielectric material portion of the memory die can be physically exposed, and external bonding pads can be formed thereupon.

公开(公告)号：US11069703B2

公开(公告)日：2021-07-20

申请号：US16291504

申请日：2019-03-04

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Akio Nishida ,  Mitsuteru Mushiga ,  Zhixin Cui

IPC: H01L27/11582 ,  H01L23/00 ,  H01L23/528 ,  H01L23/48 ,  H01L25/00 ,  H01L21/768 ,  H01L21/311 ,  H01L27/11556 ,  H01L25/065 ,  H01L27/11519 ,  H01L27/11565

Abstract: A memory die including a three-dimensional array of memory elements and a logic die including a peripheral circuitry that support operation of the three-dimensional array of memory elements can be bonded by die-to-die bonding to provide a bonded assembly. External bonding pads for the bonded assembly can be provided by forming recess regions through the memory die or through the logic die to physically expose metal interconnect structures within interconnect-level dielectric layers. The external bonding pads can include, or can be formed upon, a physically exposed subset of the metal interconnect structures. Alternatively or additionally, laterally-insulated external connection via structures can be formed through the bonded assembly to multiple levels of the metal interconnect structures. Further, through-dielectric external connection via structures extending through a stepped dielectric material portion of the memory die can be physically exposed, and external bonding pads can be formed thereupon.

公开(公告)号：US10892267B2

公开(公告)日：2021-01-12

申请号：US15950616

申请日：2018-04-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mitsuteru Mushiga ,  Kenji Sugiura ,  Hisakazu Otoi ,  Shigehisa Inoue ,  Yuki Fukuda

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/1157 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11573 ,  H01L21/28 ,  H01L27/11565 ,  H01L27/11575 ,  H01L21/762 ,  H01L27/11519 ,  H01L27/11526

Abstract: A contact via structure vertically extending through an alternating stack of insulating layers and electrically conductive layers is provided in a staircase region having stepped surfaces. The contact via structure is electrically isolated from each electrically conductive layer of the alternating stack except for an electrically conductive layer that directly underlies a horizontal interface of the stepped surfaces. A laterally-protruding portion of the contact via structure contacts an annular top surface of the electrically conductive layer. The electrical isolation can be provided by a ribbed insulating spacer that includes laterally-protruding annular rib regions at levels of the insulating layers, or can be provided by annular insulating spacers located at levels of the electrically conductive layers. The contact via structure can contact a top surface of an underlying metal interconnect structure that overlies a substrate to provide an electrically conductive path.

公开(公告)号：US10714497B1

公开(公告)日：2020-07-14

申请号：US16291457

申请日：2019-03-04

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Akio Nishida ,  Mitsuteru Mushiga

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L25/18 ,  H01L21/768 ,  H01L27/11573 ,  H01L21/28 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556

Abstract: A memory die including a three-dimensional array of memory elements and a logic die including a peripheral circuitry that support operation of the three-dimensional array of memory elements can be bonded by die-to-die bonding to provide a bonded assembly. External bonding pads for the bonded assembly can be provided by forming recess regions through the memory die or through the logic die to physically expose metal interconnect structures within interconnect-level dielectric layers. The external bonding pads can include, or can be formed upon, a physically exposed subset of the metal interconnect structures. Alternatively or additionally, laterally-insulated external connection via structures can be formed through the bonded assembly to multiple levels of the metal interconnect structures. Further, through-dielectric external connection via structures extending through a stepped dielectric material portion of the memory die can be physically exposed, and external bonding pads can be formed thereupon.

公开(公告)号：US10586803B2

公开(公告)日：2020-03-10

申请号：US16023289

申请日：2018-06-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mitsuteru Mushiga ,  Hisakazu Otoi ,  Kenji Sugiura ,  Zhixin Cui ,  Kiyohiko Sakakibara

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L21/28 ,  H01L27/11565 ,  H01L27/11529 ,  H01L27/11573 ,  H01L27/11519

Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a patterned template structure around memory openings in a drain-select-level above the alternating stack, forming drain-select-level isolation structures in trenches in the patterned template structure, forming memory stack structures in the memory openings extending through the alternating stack, where each of the memory stack structures includes a memory film and a vertical semiconductor channel, replacing the sacrificial material layers with word lines, and separately replacing the patterned template structure with a drain select gate electrode.

公开(公告)号：US20190326307A1

公开(公告)日：2019-10-24

申请号：US16023866

申请日：2018-06-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mitsuteru Mushiga ,  Hisakazu Otoi ,  Kenji Sugiura

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a patterned template structure around memory openings in a drain-select-level above the alternating stack, forming drain-select-level isolation structures in trenches in the patterned template structure, forming memory stack structures in the memory openings extending through the alternating stack, where each of the memory stack structures includes a memory film and a vertical semiconductor channel, replacing the sacrificial material layers with word lines, and separately replacing the patterned template structure with a drain select gate electrode.

公开(公告)号：US20190034125A1

公开(公告)日：2019-01-31

申请号：US15659447

申请日：2017-07-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jongsun Sel ,  Mitsuteru Mushiga ,  Toshihiro Iizuka ,  Akio Nishida ,  Tuan Pham

IPC: G06F3/06 ,  G11C7/10 ,  G06F12/02

Abstract: A method is provided that includes forming a bit line above the substrate, the bit line disposed in a first direction, after forming the bit line, forming a word line above a substrate, the word line disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material including a semiconductor material layer and a conductive oxide material layer between the word line and the bit line, and forming a memory cell including the nonvolatile memory material at an intersection of the bit line and the word line.

公开(公告)号：US20180350879A1

公开(公告)日：2018-12-06

申请号：US15610918

申请日：2017-06-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jongsun Sel ,  Tuan Pham ,  Mitsuteru Mushiga ,  Yoshihiro Ikeda ,  Daewung Kang ,  Akio Nishida

IPC: H01L27/24 ,  H01L27/11582 ,  H01L27/1157 ,  H01L23/522 ,  H01L21/768 ,  H01L45/00

CPC classification number: H01L27/2481 ,  H01L21/76879 ,  H01L23/5226 ,  H01L27/1157 ,  H01L27/11582 ,  H01L45/16

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, an array of memory structures, conductive structures located between a substrate and the alternating stack, conductive via structures, including an upper portion that overlies and contacts a top surface of a respective one of the electrically conductive layers, and a lower portion that underlies and is adjoined to the upper portion, contacts a top surface of a respective one of the conductive structures, and is electrically insulated from the rest of the electrically conductive layers. Inner, outer and intermediate dielectric spacers laterally surround a respective one of the conductive via structures.