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    Quick pass write programming techniques in a memory device
    21.
    发明授权
    Quick pass write programming techniques in a memory device 有权

    公开(公告)号：US11887677B2

    公开(公告)日：2024-01-30

    申请号：US17701365

    申请日：2022-03-22

    Applicant: SanDisk Technologies LLC

    Inventor： Muhammad Masuduzzaman ,  Deepanshu Dutta ,  Gerrit Jan Hemink

    IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  H10B41/27 ,  H10B43/27

    CPC classification number: G11C16/3459 ,  G11C16/0483 ,  G11C16/10 ,  H10B41/27 ,  H10B43/27

    Abstract: The memory device includes a controller that is configured to program the memory cells of a selected word line in a plurality of program-verify iterations. During a verify portion at least one of the program-verify iterations, the controller determines a threshold voltage of at least one memory cell relative to a first verify low voltage VL1, a second verify low voltage VL2, and a verify high voltage VH associated with a data state being programmed. The controller also maintains a count of program-verify iterations since the at least one memory cell passed a verify high voltage of a previously programmed data state or discharges a sense node through a channel including the at least one memory cell and compares a discharge time to predetermined sense times associated with the first and second verify low voltages and with the verify high voltage.

    Enhanced multistate verify techniques in a memory device
    22.
    发明授权
    Enhanced multistate verify techniques in a memory device 有权

    公开(公告)号：US11322213B2

    公开(公告)日：2022-05-03

    申请号：US16899965

    申请日：2020-06-12

    Applicant: SanDisk Technologies LLC

    Inventor： Muhammad Masuduzzaman ,  Deepanshu Dutta

    IPC: G11C16/26 ,  G11C16/14 ,  G11C16/34 ,  G11C16/04

    Abstract: A method comprises determining a verify voltage for a next iteration of a verify operation to be performed on memory cells a first set of memory cells of a selected word line, and determining data states for a second set of memory cells of at least one neighboring word line. The method further comprises determining, based on the data states, a verify voltage configuration that includes bit line voltage biases or sense times, and performing the next iteration of the verify operation on the selected word line by using the verify voltage configuration to iteratively verify whether respective memory cells, of the second set of memory cells, have threshold voltages above the verify voltage, wherein determining the data states, determining the verify voltage configuration, and performing the next iteration are to be repeated until a program stop condition is satisfied.

    SINGLE-LEVEL CELL PUMP SKIP PROGRAM OPERATION PRELIMINARY PERIOD TIMING OPTIMIZATION FOR NON-VOLATILE MEMORY
    25.
    发明公开
    SINGLE-LEVEL CELL PUMP SKIP PROGRAM OPERATION PRELIMINARY PERIOD TIMING OPTIMIZATION FOR NON-VOLATILE MEMORY 审中-公开

    公开(公告)号：US20240274200A1

    公开(公告)日：2024-08-15

    申请号：US18225375

    申请日：2023-07-24

    Applicant: SanDisk Technologies LLC

    Inventor： Chin-Yi Chen ,  Muhammad Masuduzzaman ,  Xiang Yang

    IPC: G11C16/10 ,  G11C16/04 ,  G11C16/30

    CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/30

    Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and disposed in strings and configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is coupled to the word lines and the strings and is configured to successively apply one of a series of pulses of a program voltage to each selected one of the word lines to program the memory cells connected thereto during a program operation. The control means is also configured to utilize a time of a preliminary period of the program operation based on the one of the series of pulses of the program voltage being applied. The preliminary period of the program operation is before the series of pulses of the program voltage are applied to each selected one of the plurality of word lines.

    BUNDLE MULTIPLE TIMING PARAMETERS FOR FAST SLC PROGRAMMING
    26.
    发明公开
    BUNDLE MULTIPLE TIMING PARAMETERS FOR FAST SLC PROGRAMMING 审中-公开

    公开(公告)号：US20240078028A1

    公开(公告)日：2024-03-07

    申请号：US17901310

    申请日：2022-09-01

    Applicant: SanDisk Technologies LLC

    Inventor： Chin-Yi Chen ,  Muhammad Masuduzzaman ,  Xiang Yang

    IPC: G06F3/06

    CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0679

    Abstract: Technology is disclosed herein for managing timing parameters when programming memory cells. Timing parameters used sub-clocks in an MLC program mode may also be used for those same sub-clocks in a first SLC program mode. However, in a second SLC program mode a different set of timing parameters may be used for that set of sub-clocks. Using the same set of timing parameters for the MLC program mode and the first SLC program mode saves storage space. However, the timing parameters for the MLC program mode may be slower than desired for SLC programming. A different set of timing parameters may be used for the second SLC program mode to provide for faster program operation. Moreover, the different set of timing parameters used for the faster SLC program mode do not require storage of a separate set of timing parameters.

    MODIFIED VERIFY IN A MEMORY DEVICE
    30.
    发明申请
    MODIFIED VERIFY IN A MEMORY DEVICE 有权

    公开(公告)号：US20220359024A1

    公开(公告)日：2022-11-10

    申请号：US17307626

    申请日：2021-05-04

    Applicant: SanDisk Technologies LLC

    Inventor： Xue Pitner ,  Muhammad Masuduzzaman ,  Ravi Kumar

    IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08

    Abstract: The non-volatile memory includes a control circuitry that is communicatively coupled to an array of memory cells that are arranged word lines. The control circuitry is configured to program the memory cells using a multi-pass programming operation which includes a first pass and a second pass. The first pass programs the memory cells to a first number of data states, and the second pass programs the memory cells to a greater second number of data states. For at least one word line, during the second pass, a voltage that is applied to at least one memory cell is reduced from a verify voltage by an offset which is determined as a function of a data state of an adjacent memory cell of an adjacent word line and wherein the first pass but not the second pass has been completed in the adjacent word line.

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