公开(公告)号：US20230298667A1

公开(公告)日：2023-09-21

申请号：US17697252

申请日：2022-03-17

Applicant: SanDisk Technologies LLC

Inventor： Jiacen Guo ,  Xiang Yang ,  Xiaochen Zhu

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/24

CPC classification number: G11C16/10 ,  G11C16/08 ,  G11C16/24 ,  G11C16/0483

Abstract: An apparatus is provided that includes a word line coupled to a word line driver circuit, bit lines, a plurality of non-volatile memory cells each coupled to the word line and a corresponding one of the bit lines, and a control circuit coupled to the word line and the bit lines. The control circuit is configured to program the memory cells by causing the word line driver to apply a program pulse to the word line, and biasing each bit line to a corresponding bit line voltage that has a value that varies based on a distance between the word line driver and the corresponding bit line.

公开(公告)号：US20230253053A1

公开(公告)日：2023-08-10

申请号：US17667169

申请日：2022-02-08

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Kou Tei ,  Ohwon Kwon

IPC: G11C16/14 ,  G11C16/04 ,  G11C16/26 ,  G11C16/24

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/24 ,  H01L27/11556

Abstract: A memory apparatus and method of operation are provided. The memory apparatus includes memory cells connected to word lines and disposed in memory holes organized in rows grouped in strings. The memory cells are configured to retain a threshold voltage. The rows include full circle rows and semi-circle rows in which the memory holes are partially cut by a slit half etch. The memory holes of the semi-circle rows are coupled semi-circle bit lines and the memory holes of the full circle rows are coupled to full circle bit lines. A control means is configured to erase the memory cells in an erase operation. During the erase operation, the control means creates a capacitive coupling between each of the semi-circle bit lines and at least one neighboring one of the full circle bit lines to increase a semi-circle erase voltage applied to each of the semi-circle bit lines.

公开(公告)号：US11688469B2

公开(公告)日：2023-06-27

申请号：US17399498

申请日：2021-08-11

Applicant: SanDisk Technologies LLC

Inventor： Dengtao Zhao ,  Gerrit Jan Hemink ,  Xiang Yang ,  Ken Oowada ,  Guirong Liang

IPC: G11C16/04 ,  G11C16/34 ,  H01L25/18 ,  H01L23/00 ,  G11C11/56 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  H01L25/065

CPC classification number: G11C16/3427 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/08145 ,  H01L2225/06506 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: To help reduce program disturbs in non-selected NAND strings of a non-volatile memory, a sub-block based boosting scheme in introduced. For a three dimensional NAND memory structure, in which the memory cells above a joint region form an upper sub-block and memory cells below the joint region form a lower sub-block, dummy word lines in the joint region act as select gates to allow boosting at the sub-block level when the lower block is being programmed in a reverse order.

公开(公告)号：US20220415416A1

公开(公告)日：2022-12-29

申请号：US17355684

申请日：2021-06-23

Applicant: SanDisk Technologies LLC

Inventor： Abhijith Prakash ,  Xiang Yang

IPC: G11C16/34 ,  G11C16/14 ,  G11C16/10 ,  G11C16/26

Abstract: Non-volatile memory systems are disclosed. The memory systems include rows of memory holes FC-SGD and SC-SGD, the latter of which may be created by a SHE cutting operation. The SC-SGD include erase speeds slower than those of FC-SGD. In order to overcome the erase speed disparities, SC-SGD are programmed to a higher Vt as compared to FC-SGD. By programming SC-SGD to a higher Vt, the erase speed increases and matches the erase speed of FC-SGD. Further, different SC-SGDs are cut to different amounts, creating different erase speeds among SC-SGD. SC-SGDs with a greater degree/amount of cut have slower erase speeds as compared to SC-SGDs with a lesser degree/amount of cut. However, verify levels among SC-SGDs can differ to produce SC-SGDs with Vt's such that their erase speeds match with each other as well as with FC-SGD.

公开(公告)号：US20220406389A1

公开(公告)日：2022-12-22

申请号：US17349118

申请日：2021-06-16

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26

Abstract: A method for programming a memory block of a non-volatile memory structure, comprising determining whether a number of programming/erase cycles previously applied to the block exceeds a first programming/erase cycle threshold and, if the first threshold is exceeded, determining whether the number of programming/erase cycles previously applied to the block exceeds an extended programming/erase cycle threshold. Further, if the determination is made that the extended threshold is not exceeded, the method comprises applying a two-pulse per programming loop scheme to each of the outermost strings of the block and applying a single-pulse per programming loop scheme to all other strings of the block. Alternatively, or in addition thereto, relative to a programming/erase cycle threshold, one or more outermost strings of the block may be unpermitted to be further programmed, and a “sub-block” comprised of all valid strings of the block may be defined and permitted for further programming.

公开(公告)号：US11532370B1

公开(公告)日：2022-12-20

申请号：US17329304

申请日：2021-05-25

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Deepanshu Dutta

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C11/56 ,  H01L27/11565 ,  G11C16/04 ,  H01L25/065 ,  H01L27/11582

Abstract: To improve programming performance for a non-volatile memory , the verification of multiple programming levels can be performed based on a single discharge of a sensing capacitor through a selected memory cell by using different voltage levels on a second plate of the sensing capacitor: after discharging a first plate of the sensing capacitor through the selected memory cell, a result amount of charge is trapped on the first plate, which is then used to set first and second control gate voltages on a sensing transistor whose control gate is connected to the first place of the sensing capacitor based on respectively setting the second plate of the sensing capacitor to first and second voltage levels. To further improve programming performance, when the non-volatile memory stores in a multistate format, after the next to highest data state finishes programming, the next programming pulse can use a larger step size.

公开(公告)号：US20220392556A1

公开(公告)日：2022-12-08

申请号：US17337758

申请日：2021-06-03

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/24 ,  G11C16/08 ,  G11C16/30

Abstract: Non-volatile memory systems and method for managing P/E cycling is disclosed. Memory systems include multi-plane (e.g., 2-plane or 4-plane) programming operations in which new blocks within a plane replace faulty/bad blocks. Existing blocks, having undergone several P/E cycles more than the new block(s), require a lower programming voltage and are programmed using an adaptive (reduced) programming voltage. New block(s) require an additional voltage, and a delta voltage is added to the programming voltage to increase the gate-to-channel voltage. To prevent the delta voltage from over-programming the existing blocks, a voltage equal to the delta voltage is applied bit lines of the existing blocks, thereby reducing the effective gate-to-channel voltage on the existing blocks. In this manner, the same programming voltage is applied to planes in a multi-plane programming operation, and the existing blocks receive a relatively lower gate-to-channel voltage, while the new block(s) receive a relatively higher gate-to-channel voltage.

公开(公告)号：US11521677B1

公开(公告)日：2022-12-06

申请号：US17326641

申请日：2021-05-21

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Huai-yuan Tseng

IPC: G11C7/00 ,  G11C11/56 ,  G11C16/26 ,  G11C16/08 ,  G11C16/04

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and arranged in strings and configured to retain a threshold voltage. A control circuit is coupled to the word lines and strings and is configured to compute a target word line voltage including a kicking voltage to be applied to selected ones of word lines for a kick time during a read operation. The control circuit extends the kick time by a compensation time to a compensated kick time in response to determining the target word line voltage is not greater than a predetermined voltage design limit. The control circuit applies the kicking voltage to the selected ones of word lines for the compensated kick time thereby enabling a word line voltage to reach one of a plurality of reference voltages quickly without exceeding the predetermined voltage design limit.

公开(公告)号：US20220375515A1

公开(公告)日：2022-11-24

申请号：US17326641

申请日：2021-05-21

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Huai-yuan Tseng

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and arranged in strings and configured to retain a threshold voltage. A control circuit is coupled to the word lines and strings and is configured to compute a target word line voltage including a kicking voltage to be applied to selected ones of word lines for a kick time during a read operation. The control circuit extends the kick time by a compensation time to a compensated kick time in response to determining the target word line voltage is not greater than a predetermined voltage design limit. The control circuit applies the kicking voltage to the selected ones of word lines for the compensated kick time thereby enabling a word line voltage to reach one of a plurality of reference voltages quickly without exceeding the predetermined voltage design limit.

公开(公告)号：US11250917B2

公开(公告)日：2022-02-15

申请号：US16910697

申请日：2020-06-24

Applicant: SanDisk Technologies LLC

Inventor： Jianzhi Wu ,  Xiang Yang

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/34 ,  G11C16/24

Abstract: A method and system are provided for reading a non-transitory memory array. When a default read operation is performed and has failed, a dynamic sensing bit line voltage (VBLC) enhanced read or a dynamic sense time read is performed. According to the dynamic VBLC enhanced read or the dynamic sense time enhanced read, the VBLC or the sense time is increased, and a read is performed with the increased VBLC or increased sense time. If this enhanced read is unsuccessful, and if a maximum VBLC or a maximum sense time has not yet been reached, the VBLC or the sense time is increased again, and another read is performed. Once the maximum VBLC or a maximum sense time has been reached, if the read is still not successful, a read failure is reported.