公开(公告)号：US20210320013A1

公开(公告)日：2021-10-14

申请号：US17304792

申请日：2021-06-25

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yong LIU ,  Yusheng LIN ,  Liangbiao CHEN

IPC: H01L21/48 ,  H01L23/28 ,  H01L21/56 ,  H01L23/495 ,  H01L23/498

Abstract: Methods of forming semiconductor packages include providing a first insulator layer coupled with a first metallic layer. A recess is formed in the first metallic layer and a semiconductor die is mechanically coupled therein. The die is mechanically coupled with a second metallic layer and the second metallic layer is coupled with a second insulator layer. The die and layers are at least partially encapsulated to form the semiconductor package. The first and/or second metallic layers may be insulator-metal substrates, metal-insulator-metal (MIM) substrates, or may be formed of lead frames. In implementations the package does not include a spacer between the die and the first metallic layer and does not include a spacer between the die and the second metallic layer. In implementations the first insulator layer and the second insulator layer are exposed through the encapsulant or are mechanically coupled with metallic layers exposed through the encapsulant.

公开(公告)号：US20210217679A1

公开(公告)日：2021-07-15

申请号：US16740130

申请日：2020-01-10

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Tzu-Hsuan CHENG ,  Yong LIU ,  Liangbiao CHEN

IPC: H01L23/367 ,  H01L21/52 ,  H01L21/56 ,  H01L23/373 ,  H01L23/495 ,  H01L23/00 ,  H05K7/20

Abstract: A semiconductor device module may include a leadframe spacer that provides the functions of both a leadframe and a spacer, while enabling a double-sided cooling configuration. Such a leadframe spacer may include a leadframe surface that provides a die attach pad (DAP) that is shared by at least two semiconductor devices. The leadframe spacer may include at least one downset, where the semiconductor devices may be attached within a recess defined by the at least one downset. A first substrate may be connected to a first side of the leadframe. A second substrate may be connected to downset surfaces of the at least one downset, and positioned for further connection to the semiconductor devices in a double-sided assembly.

公开(公告)号：US20210134606A1

公开(公告)日：2021-05-06

申请号：US16674279

申请日：2019-11-05

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yong LIU ,  Yusheng LIN ,  Liangbiao CHEN

IPC: H01L21/48 ,  H01L23/28 ,  H01L23/495 ,  H01L21/56

Abstract: Methods of forming semiconductor packages include providing a first insulator layer coupled with a first metallic layer. A recess is formed in the first metallic layer and a semiconductor die is mechanically coupled therein. The die is mechanically coupled with a second metallic layer and the second metallic layer is coupled with a second insulator layer. The die and layers are at least partially encapsulated to form the semiconductor package. The first and/or second metallic layers may be insulator-metal substrates, metal-insulator-metal (MIM) substrates, or may be formed of lead frames. In implementations the package does not include a spacer between the die and the first metallic layer and does not include a spacer between the die and the second metallic layer. In implementations the first insulator layer and the second insulator layer are exposed through the encapsulant or are mechanically coupled with metallic layers exposed through the encapsulant.

公开(公告)号：US20240282668A1

公开(公告)日：2024-08-22

申请号：US18172904

申请日：2023-02-22

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yong LIU ,  Liangbiao CHEN ,  Yusheng LIN ,  Chee Hiong CHEW

IPC: H01L23/433 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/4334 ,  H01L21/4882 ,  H01L21/565 ,  H01L23/3107

Abstract: A protective dam can relieve stress in a chip assembly of a high-power semiconductor device module used in electric vehicle or industrial applications. Some chip assemblies that incorporate copper spacers for thermal dissipation can cause the device module to become vulnerable to cracking. Adding a protective dam can absorb stress to prevent damage to materials surrounding the chip assembly. Various types of protective dams are presented, including high profile flexible protective dams, low profile flexible protective dams, metallic protective dams, and integral protective dams. The protective dams can be incorporated into a high-power semiconductor device module that features single sided or dual sided cooling via direct bond metal structures.

公开(公告)号：US20240030093A1

公开(公告)日：2024-01-25

申请号：US18479565

申请日：2023-10-02

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Leo GU ,  Sixin JI ,  Jie CHANG ,  Keunhyuk LEE ,  Yong LIU

IPC: H01L23/373 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/3735 ,  H01L24/32 ,  H01L21/4871 ,  H01L24/83 ,  H01L2224/83815 ,  H01L2224/32237

Abstract: In one general aspect, a method can include forming a recess and a mesa in a metal layer associated with a substrate, and disposing a first portion of a conductive-bonding component on the mesa and a second portion of the conductive-bonding component in the recess. The method can include disposing a semiconductor component on the conductive-bonding component such that the second portion of the conductive-bonding component is disposed between an edge of the semiconductor component and a bottom surface of the recess.

公开(公告)号：US20220208653A1

公开(公告)日：2022-06-30

申请号：US17136299

申请日：2020-12-29

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yong LIU ,  Qing YANG

IPC: H01L23/492 ,  H01L23/373 ,  H01L23/00

Abstract: A dual-side cooling (DSC) semiconductor package includes a first metal-insulator-metal (MIM) substrate having a first insulator layer, first metallic layer, and second metallic layer. A second MIM substrate includes a second insulator layer, third metallic layer, and fourth metallic layer. The third metallic layer includes a first portion having a first contact area and a second portion, electrically isolated from the first portion, having a second contact area. A semiconductor die is coupled with the second metallic layer and is directly coupled with the third metallic layer through one or more solders, sintered layers, electrically conductive tapes, solderable top metal (STM) layers, and/or under bump metal (UBM) layers. The first contact area is electrically coupled with a first electrical contact of the die and the second contact area is electrically coupled with a second electrical contact of the die. The first and fourth metallic layers are exposed through an encapsulant.