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    PACKAGE WITH MOLDING CAVITY
    1.
    发明申请
    PACKAGE WITH MOLDING CAVITY 有权

    公开(公告)号：US20240371659A1

    公开(公告)日：2024-11-07

    申请号：US18311100

    申请日：2023-05-02

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Yong LIU ,  Liangbiao CHEN ,  Chee Hiong CHEW

    IPC: H01L21/56 ,  H01L21/477 ,  H01L23/00 ,  H01L23/373 ,  H01L23/495

    Abstract: A high-power semiconductor device module is implemented with a cavity in the molding package. The cavity reduces a volume of the molding compound, preventing an accumulation of stress in the module, and associated warpage of the package. Chip assemblies within the module are designed to fit within the cavity, so that semiconductor dies, and sensing devices therein are protected from damage during a sintering process in which the module is mounted to a heat sink. After the sintering process, the cavity can be sealed with a gel material. The molding package described herein can also enhance reliability of the module during operation, ensuring that the product is robust for electric and hybrid electric vehicle applications.

    PROTECTION DAM FOR A POWER MODULE WITH SPACERS
    2.
    发明公开
    PROTECTION DAM FOR A POWER MODULE WITH SPACERS 审中-公开

    公开(公告)号：US20240282668A1

    公开(公告)日：2024-08-22

    申请号：US18172904

    申请日：2023-02-22

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Yong LIU ,  Liangbiao CHEN ,  Yusheng LIN ,  Chee Hiong CHEW

    IPC: H01L23/433 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

    CPC classification number: H01L23/4334 ,  H01L21/4882 ,  H01L21/565 ,  H01L23/3107

    Abstract: A protective dam can relieve stress in a chip assembly of a high-power semiconductor device module used in electric vehicle or industrial applications. Some chip assemblies that incorporate copper spacers for thermal dissipation can cause the device module to become vulnerable to cracking. Adding a protective dam can absorb stress to prevent damage to materials surrounding the chip assembly. Various types of protective dams are presented, including high profile flexible protective dams, low profile flexible protective dams, metallic protective dams, and integral protective dams. The protective dams can be incorporated into a high-power semiconductor device module that features single sided or dual sided cooling via direct bond metal structures.

    LEADFRAME SPACER FOR DOUBLE-SIDED POWER MODULE
    4.
    发明申请
    LEADFRAME SPACER FOR DOUBLE-SIDED POWER MODULE 有权

    公开(公告)号：US20210398874A1

    公开(公告)日：2021-12-23

    申请号：US17447011

    申请日：2021-09-07

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Tzu-Hsuan CHENG ,  Yong LIU ,  Liangbiao CHEN

    IPC: H01L23/367 ,  H01L21/52 ,  H01L21/56 ,  H01L23/373 ,  H01L23/495 ,  H05K7/20 ,  H01L23/00

    Abstract: A semiconductor device module may include a leadframe spacer that provides the functions of both a leadframe and a spacer, while enabling a double-sided cooling configuration. Such a leadframe spacer may include a leadframe surface that provides a die attach pad (DAP) that is shared by at least two semiconductor devices. The leadframe spacer may include at least one downset, where the semiconductor devices may be attached within a recess defined by the at least one downset. A first substrate may be connected to a first side of the leadframe. A second substrate may be connected to downset surfaces of the at least one downset, and positioned for further connection to the semiconductor devices in a double-sided assembly.

    SPACER WITH PATTERN LAYOUT FOR DUAL SIDE COOLING POWER MODULE
    6.
    发明申请
    SPACER WITH PATTERN LAYOUT FOR DUAL SIDE COOLING POWER MODULE 有权

    公开(公告)号：US20220208635A1

    公开(公告)日：2022-06-30

    申请号：US17136286

    申请日：2020-12-29

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Yong LIU ,  Liangbiao CHEN ,  Yusheng LIN ,  Chee Hiong CHEW

    IPC: H01L23/367 ,  H01L23/373 ,  H01L21/48

    Abstract: A method includes bonding a device die to a direct bonded metal (DBM) substrate, bonding a spacer block to the device die, and at least partially reducing coefficient of thermal expansion (CTE) mismatches between the DBM substrate, the spacer block and the device die. At least partially reducing the CTE mismatches between the DBM substrate, the spacer block and the device die includes at least one of: disposing an arrangement of pillars and grooves in a surface region of the spacer block coupled to the device die, disposing at least one cavity in the spacer block, and disposing a groove in an outer conductive layer of the DBM substrate.

    SEMICONDUCTOR PACKAGES AND RELATED METHODS
    8.
    发明公开
    SEMICONDUCTOR PACKAGES AND RELATED METHODS 审中-公开

    公开(公告)号：US20240355638A1

    公开(公告)日：2024-10-24

    申请号：US18760515

    申请日：2024-07-01

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Yong LIU ,  Yusheng LIN ,  Liangbiao CHEN

    IPC: H01L21/48 ,  H01L21/56 ,  H01L23/28 ,  H01L23/495 ,  H01L23/498

    CPC classification number: H01L21/4821 ,  H01L21/56 ,  H01L23/28 ,  H01L23/49534 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/49861

    Abstract: Methods of forming semiconductor packages include providing a first insulator layer coupled with a first metallic layer. A recess is formed in the first metallic layer and a semiconductor die is mechanically coupled therein. The die is mechanically coupled with a second metallic layer and the second metallic layer is coupled with a second insulator layer. The die and layers are at least partially encapsulated to form the semiconductor package. The first and/or second metallic layers may be insulator-metal substrates, metal-insulator-metal (MIM) substrates, or may be formed of lead frames. In implementations the package does not include a spacer between the die and the first metallic layer and does not include a spacer between the die and the second metallic layer. In implementations the first insulator layer and the second insulator layer are exposed through the encapsulant or are mechanically coupled with metallic layers exposed through the encapsulant.

    SEMICONDUCTOR PACKAGES AND RELATED METHODS
    10.
    发明申请
    SEMICONDUCTOR PACKAGES AND RELATED METHODS 有权

    公开(公告)号：US20210320013A1

    公开(公告)日：2021-10-14

    申请号：US17304792

    申请日：2021-06-25

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Yong LIU ,  Yusheng LIN ,  Liangbiao CHEN

    IPC: H01L21/48 ,  H01L23/28 ,  H01L21/56 ,  H01L23/495 ,  H01L23/498

    Abstract: Methods of forming semiconductor packages include providing a first insulator layer coupled with a first metallic layer. A recess is formed in the first metallic layer and a semiconductor die is mechanically coupled therein. The die is mechanically coupled with a second metallic layer and the second metallic layer is coupled with a second insulator layer. The die and layers are at least partially encapsulated to form the semiconductor package. The first and/or second metallic layers may be insulator-metal substrates, metal-insulator-metal (MIM) substrates, or may be formed of lead frames. In implementations the package does not include a spacer between the die and the first metallic layer and does not include a spacer between the die and the second metallic layer. In implementations the first insulator layer and the second insulator layer are exposed through the encapsulant or are mechanically coupled with metallic layers exposed through the encapsulant.

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