ISOLATED 3D SEMICONDUCTOR DEVICE PACKAGE

    公开(公告)号:US20220020740A1

    公开(公告)日:2022-01-20

    申请号:US16948796

    申请日:2020-10-01

    Abstract: Described implementations provide wireless, surface mounting of at least two semiconductor devices on opposed surfaces of a leadframe, to provide an isolated, three-dimensional (3D) configuration. The described implementations minimize electrical failures, even for very high voltage applications, while enabling low inductance and high current. Resulting semiconductor device packages have mounting surfaces that provide desired levels of isolation and insulation, while still enabling straightforward mounting techniques, such as soldering, as well as high levels of thermal reliability.

    FLEXIBLE CLIP
    4.
    发明公开
    FLEXIBLE CLIP 审中-公开

    公开(公告)号:US20230326902A1

    公开(公告)日:2023-10-12

    申请号:US17658885

    申请日:2022-04-12

    CPC classification number: H01L24/72 H01L24/90

    Abstract: A clip preform includes a die contact portion and an aligner structure. An intermediate portion connects the die contact portion to a lead contact portion in the aligner structure. The die contact portion is configured to contact a semiconductor die. The aligner structure is configured to attach the lead contact portion to a lead post. The die contact portion, the intermediate portion, and the aligner structure form a structure of a primary clip for connecting the semiconductor die to the lead post. The clip preform is severable by removing parts of the die contact portion and the intermediate portion of the clip preform to form a secondary clip for connecting the semiconductor die to the lead post. The aligner structure, a remaining part of the die contact portion, and a remaining part of the intermediate portion of the clip preform form a structure of the secondary clip.

    HIGH POWER MODULE SEMICONDUCTOR PACKAGE WITH MULTIPLE SUBMODULES

    公开(公告)号:US20190221493A1

    公开(公告)日:2019-07-18

    申请号:US15874355

    申请日:2018-01-18

    Abstract: In one general aspect, a package can include a first submodule including a first semiconductor die coupled to a first substrate and a first spacer, and disposed between the first spacer and the first substrate. The first submodule includes a second spacer disposed lateral to the first semiconductor die. The package includes a second submodule including a second semiconductor die coupled to a second substrate and a third spacer, and disposed between the third spacer and the second substrate. The second submodule includes a fourth spacer disposed lateral to the second semiconductor die. The package includes an inter-module layer disposed between the first submodule and the second submodule. The first spacer of the first submodule is electrically coupled to the fourth spacer of the second-submodule via the inter-module layer. The second spacer of the first submodule is electrically coupled to the third spacer of the second-submodule via the inter-module layer.

    POWER SEMICONDUCTOR DEVICE PACKAGE
    10.
    发明申请

    公开(公告)号:US20200258824A1

    公开(公告)日:2020-08-13

    申请号:US16513437

    申请日:2019-07-16

    Abstract: In a general aspect, an apparatus can include a leadframe. The apparatus can also include a first semiconductor die coupled with a first side of a first portion of the leadframe, and a second semiconductor die coupled with a second side of the first portion of the leadframe. The apparatus can also include a first substrate coupled with a second side of the first semiconductor die. The first substrate can be further coupled with a first side of a second portion of the leadframe and a first side of a third portion of the leadframe. The apparatus can also further include a second substrate coupled with a second side of the second semiconductor die. The second substrate can be further coupled with a second side of the second portion of the leadframe and a second side of the third portion of the leadframe.

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