公开(公告)号：US20190013060A1

公开(公告)日：2019-01-10

申请号：US15941194

申请日：2018-03-30

Applicant: SK hynix Inc. ,  Seoul National University R&DB Foundation

Inventor： Deog-Kyoon JEONG ,  Jung Min YOON ,  Hyungrok DO

IPC: G11C11/4091 ,  H03F3/45 ,  G11C11/4099 ,  H03F1/02 ,  G11C11/4094

Abstract: An integrated circuit includes: an amplifier circuit including a first inverter and a second inverter to amplify a voltage difference between a first line and a second line; a replica amplifier circuit including a first replica inverter having an input terminal and an output terminal which are coupled to a second replica line and replicating the first inverter, and that includes a second replica inverter having an input terminal and an output terminal which are coupled to a first replica line and replicating the second inverter; and a current control circuit suitable for controlling an amount of a current sourced to the replica amplifier circuit and an amount of a current sunken from the replica amplifier circuit based on comparison of an average level between a voltage of the first replica line and a voltage of the second replica line with a level of a target voltage.

公开(公告)号：US20190007000A1

公开(公告)日：2019-01-03

申请号：US15941173

申请日：2018-03-30

Applicant: SK hynix Inc. ,  Seoul National University R&DB Foundation

Inventor： Deog-Kyoon JEONG ,  Jung Min YOON

IPC: H03F1/30 ,  H03F1/02 ,  H03F3/45 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096

CPC classification number: H03F1/301 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  H03F1/0205 ,  H03F3/45179 ,  H03F3/45744 ,  H03F2200/375 ,  H03F2200/87 ,  H03F2203/45018

Abstract: An amplifier circuit includes: a first inverter and a second inverter coupled in a cross-coupled form during an amplification operation and suitable for amplifying a voltage difference between a first line and a second line; a first isolation switch suitable for electrically connecting the first line and an output terminal of the first inverter to each other; a second isolation switch suitable for electrically connecting the second line and an output terminal of the second inverter to each other; and an equalizing switch suitable for electrically connecting the output terminal of the first inverter and the output terminal of the second inverter to each other, wherein before the amplification operation, a first offset compensation operation for turning on the second isolation switch and the equalizing switch and a second offset compensation operation for turning on the first isolation switch and the equalizing switch are performed.

公开(公告)号：US20180343149A1

公开(公告)日：2018-11-29

申请号：US15845318

申请日：2017-12-18

Applicant: SK hynix Inc. ,  Seoul National University R&DB Foundation

Inventor： Suhwan KIM ,  Min-Chang KIM ,  Deog-Kyoon JEONG

IPC: H04L25/03 ,  H04L25/02 ,  H04B1/12

CPC classification number: H04L25/03063 ,  H04B1/123 ,  H04L25/0202 ,  H04L25/03885

Abstract: A signal receiver circuit may include: a receiver suitable for generating a received signal based on comparison of an input signal with a reference voltage during a normal operation and based on comparison of the input signal with a target voltage during a training operation; a compensator suitable for applying a weight to the received signal to compensate for the input signal; and a weight adjuster suitable for adjusting the weight based on a level of the received signal during the training operation, wherein during the training operation, the input signal toggles between first and second levels, and the receiver is enabled when the input signal is at the first level.

公开(公告)号：US20220247415A1

公开(公告)日：2022-08-04

申请号：US17512483

申请日：2021-10-27

Applicant: SK hynix Inc. ,  Seoul National University R&DB Foundation

Inventor： Hyojun KIM ,  Deog-Kyoon JEONG

IPC: H03L7/093

Abstract: A phase-locked loop includes a bias circuit controlling a first bias current between a first power source and a first node according to a bias control signal; an oscillation circuit coupled between the first node and a second power source and generating an oscillation signal according to a current from the first node; a duplicate bias circuit controlling a second bias current between the first power source and a second node according to the bias control signal; an equivalent impedance circuit coupled between the second node and the second power source; a comparator circuit comparing voltages of the first node and the second node; a first variable current circuit controlling a current between the first node and the second power source; and a second variable current circuit controlling a current between the second node and the second power source.

公开(公告)号：US20220216859A1

公开(公告)日：2022-07-07

申请号：US17316329

申请日：2021-05-10

Applicant: SK hynix Inc. ,  Seoul National University R&DB Foundation

Inventor： Soyeong SHIN ,  Yongjae LEE ,  Jiheon PARK ,  Deog-Kyoon JEONG

IPC: H03K5/135

Abstract: A semiconductor device includes a delay compensation circuit and a bias control circuit. The delay compensation circuit includes a variable delay circuit configured to generate an output signal by delaying an input signal and configured to compensate, according to a first bias control signal, for delay fluctuation caused by fluctuation of a power supply voltage between a first power source and a second power source. The bias control circuit is configured to generate the first bias control signal to compensate for the delay fluctuation.

公开(公告)号：US20200075065A1

公开(公告)日：2020-03-05

申请号：US16545805

申请日：2019-08-20

Applicant: SK hynix Inc. ,  Seoul National University R&DB Foundation

Inventor： Deog-Kyoon JEONG ,  Jung Min YOON ,  Hyungrok DO ,  Dae-Hyun KOH

IPC: G11C7/06 ,  H03F1/02 ,  H03F3/16 ,  G11C11/22

Abstract: A BLSA circuit includes a first inverter disposed between a first sensing node and a second inner bit line, a second inverter disposed between a second sensing node and a first inner bit line, a first capacitor disposed between a first bit line and the first sensing node, a second capacitor disposed between a second bit line and the second sensing node, a first offset canceling switch for electrically coupling the first inner bit line with the second sensing node during an offset canceling operation, a second offset canceling switch for electrically coupling the second inner bit line with the first sensing node during the offset canceling operation, a first isolation switch for electrically coupling the first bit line with the first inner bit line, and a second isolation switch for electrically coupling the second bit line with the second inner bit line.

公开(公告)号：US20190305819A1

公开(公告)日：2019-10-03

申请号：US16221720

申请日：2018-12-17

Applicant: SK hynix Inc. ,  Seoul National University R&DB Foundation

Inventor： Deog-Kyoon JEONG ,  Suhwan KIM ,  Sung-Phil CHOI

IPC: H04B3/487 ,  H04B3/32 ,  H04B3/462

Abstract: An integrated circuit may include: a first transmission line; a second transmission line; a first compensator circuit suitable for generating a first compensation signal by delaying and differentiating a signal transferred through the second transmission line; a second compensator circuit suitable for generating a second compensation signal by delaying and differentiating a signal transferred through the first transmission line; a first receiver circuit suitable for receiving the signal transferred through the first transmission line, and compensating for the signal transferred through the first transmission line using the first compensation signal; and a second receiver circuit suitable for receiving the signal transferred through the second transmission line, and compensating for the signal transferred through the second transmission line using the second compensation signal.

公开(公告)号：US20190268005A1

公开(公告)日：2019-08-29

申请号：US16237040

申请日：2018-12-31

Applicant: SK hynix Inc. ,  Seoul National University R&DB Foundation

Inventor： Suhwan KIM ,  Deog-Kyoon JEONG ,  Sang-Yoon LEE ,  Joo-Hyung CHAE ,  Chang-Ho HYUN

IPC: H03L7/089 ,  H03L7/087 ,  H04L7/033 ,  H04L7/00

Abstract: A data receiver circuit may include: a delay circuit suitable for delaying first and second strobe signals and generating delayed first and second strobe signals; a first receiver circuit suitable for sampling data in synchronization with the delayed first strobe signal; a second receiver circuit suitable for sampling the data in synchronization with the delayed second strobe signal; an enable signal generation circuit suitable for generating an enable signal indicating whether the data transitioned; a transition level generation circuit suitable for generating a transition level signal indicating a transition direction of the data; a phase shift circuit suitable for shifting the phase of the delayed first strobe signal by a set degree and generating a shifted first strobe signal; a sampling circuit suitable for sampling the data in synchronization with the shifted first strobe signal and generating a sampling result; and a control logic suitable for changing a delay value of the delay circuit in response to the transition level signal and the sampling result of the sampling circuit, when the enable signal is activated.

公开(公告)号：US20190131962A1

公开(公告)日：2019-05-02

申请号：US16149687

申请日：2018-10-02

Applicant: SK hynix Inc. ,  Seoul National University R&DB Foundation

Inventor： Deog-Kyoon JEONG ,  Suhwan KIM ,  Joo-Hyung CHAE

IPC: H03K5/26 ,  H03K3/03 ,  H03K17/687 ,  H03H7/06 ,  G01R25/00

CPC classification number: H03K5/26 ,  G01R25/00 ,  H03H7/06 ,  H03K3/0315 ,  H03K17/687

Abstract: A duty cycle detector includes a first ring oscillator suitable for including an odd number of first inverters and generating a first periodic signal by using the first inverters, at least one inverter among the first inverters being enabled during a time interval when a clock has a first value, a second ring oscillator including an odd number of second inverters and suitable for generating a second periodic signal using the second inverters, at least one inverter among the second inverters being enabled during a time interval when the clock has a second value. The duty cycle detector further includes a frequency comparator suitable for comparing a frequency of the first periodic signal with a frequency of the second periodic signal and generating a duty cycle detection signal of the clock.

公开(公告)号：US20190081619A1

公开(公告)日：2019-03-14

申请号：US15965505

申请日：2018-04-27

Applicant: SK hynix Inc. ,  Seoul National University R&DB Foundation

Inventor： Suhwan KIM ,  Joo-Hyung CHAE ,  Deog-Kyoon JEONG

IPC: H03K5/156

Abstract: A duty cycle correction circuit includes a first inverter suitable for driving a second clock in response to a first clock; a second inverter suitable for driving the first clock in response to the second clock; and a duty cycle detector suitable for detecting a duty cycle of the first clock or the second clock, wherein driving forces of one or more inverters among the first inverter and the second inverter are controlled based on a duty detection result of the duty cycle detector.