Abstract:
Provided is a solid-state image pickup device including: a plurality of pixels, each of which includes a photoelectric conversion portion and a pixel transistor formed in a front surface side of a substrate, wherein a rear surface side of the substrate is set as a light receiving plane of the photoelectric conversion portion; and an element, which becomes a passive element or an active element, which is disposed in the front surface side of the substrate so as to be superimposed on the photoelectric conversion portion.
Abstract:
Provided is a solid-state image pickup device including: a plurality of pixels, each of which includes a photoelectric conversion portion and a pixel transistor formed in a front surface side of a substrate, wherein a rear surface side of the substrate is set as a light receiving plane of the photoelectric conversion portion; and an element, which becomes a passive element or an active element, which is disposed in the front surface side of the substrate so as to be superimposed on the photoelectric conversion portion.
Abstract:
A solid-state imaging device includes a pixel array section and a signal processing section. The pixel array section is configured to include a plurality of arranged rectangular pixels, each of which has different sizes in the vertical and horizontal directions, and a plurality of adjacent ones of which are combined to form a square pixel having the same size in the vertical and horizontal directions. The signal processing section is configured to perform a process of outputting, as a single signal, a plurality of signals read out from the combined plurality of rectangular pixels.
Abstract:
A solid-state imaging device includes a pixel array section and a signal processing section. The pixel array section is configured to include a plurality of arranged rectangular pixels, each of which has different sizes in the vertical and horizontal directions, and a plurality of adjacent ones of which are combined to form a square pixel having the same size in the vertical and horizontal directions. The signal processing section is configured to perform a process of outputting, as a single signal, a plurality of signals read out from the combined plurality of rectangular pixels.
Abstract:
In a solid-state image sensing apparatus of an addressing method, a clock-conversion part generates a high-speed clock signal having a frequency two times or more the frequency of a low-speed clock signal. A signal processing part receives 10-bit pixel data through a horizontal signal line, performs predetermined signal processing, and passes parallel-format data to a switching part. The switching part selects each one bit of the parallel-format 10-bit data in a predetermined sequence to output from an output terminal using the high-speed clock signal from the clock-conversion part as a switching command, thus converts the parallel-format data into serial-format data, and passes it to an output buffer. The output buffer externally outputs differential output of normal video data and inverted video data individually from output terminals. Accordingly, the problems in power consumption, noises, and unnecessary radiation are solved, and higher-speed output is achieved.
Abstract:
An MOS type solid state imaging device in which unit pixels 10 each having a photodiode 11, a transfer transistor 12 for transferring the signal of the photodiode 11 to a floating node N11, an amplifier transistor 13 for outputting the signal of the floating node N11 to a vertical signal line 22, and a reset transistor 14 for resetting the floating node N11 are arrayed in a matrix and in which a gate voltage of the reset transistor 14 is controlled by three values of a power source potential (for example 3V), a ground potential (0V), and a negative power source potential (for example −1V).
Abstract:
An MOS type solid state imaging device in which unit pixels 10 each having a photodiode 11, a transfer transistor 12 for transferring the signal of the photodiode 11 to a floating node N11, an amplifier transistor 13 for outputting the signal of the floating node N11 to a vertical signal line 22, and a reset transistor 14 for resetting the floating node N11 are arrayed in a matrix and in which a gate voltage of the reset transistor 14 is controlled by three values of a power source potential (for example 3V), a ground potential (OV), and a negative power source potential (for example −1V).
Abstract:
A solid-state image pickup device including a plurality of pixels and a scanning unit. Each pixel includes a photoelectric conversion element and a charge accumulation region. The scanning unit is configured to read a first signal from a charge accumulation region. The scanning unit is configured to read a second signal from the charge accumulation region. The first signal corresponds to an accumulation of signal charges during a first period, while the second signal corresponds to another accumulation of signal charges during a second period.
Abstract:
A solid state image pickup device is provided that includes a pixel array unit having a plurality of pixels and a signal processing circuit that has a capacitor operatively configured to process a respective signal output from each of the plurality of pixels. The capacitor is operatively configured as a stacked capacitor or a trench capacitor.
Abstract:
a CMOS image sensor including a pixel array unit having pixels arranged in even-numbered pixel rows and odd-numbered pixel rows. A reading operation performed such that a first signal of a first pixel group is read in a first accumulation time, and a second signal of a second pixel group is read in a second accumulation time shorter than said first accumulation time.