公开(公告)号：US20240056091A1

公开(公告)日：2024-02-15

申请号：US18363582

申请日：2023-08-01

Applicant: STMicroelectronics International N.V.

Inventor： Ankur BAL ,  Jeet Narayan TIWARI

IPC: H03M1/06 ,  H03M1/12 ,  H03M1/10

CPC classification number: H03M1/0626 ,  H03M1/1255 ,  H03M1/1071

Abstract: An integrated circuit includes a plurality of ADC channels. During a calibration process of the ADC channels, the integrated circuit utilizes derivative filters to calculate a phase difference between the ADC channels. During a calibration process, the integrated circuit utilizes clock phase alignment circuits to align the phases of the ADC channels based on the outputs of the derivative filters.

公开(公告)号：US20230259158A1

公开(公告)日：2023-08-17

申请号：US18165855

申请日：2023-02-07

Applicant: STMicroelectronics International N.V.

Inventor： Ankur BAL ,  Sharad GUPTA ,  Anupam JAIN

IPC: G06F1/12 ,  G06F1/08

CPC classification number: G06F1/12 ,  G06F1/08

Abstract: An integrated circuit includes a first subsystem including a first clock generator configured to generate a first clock signal. The integrated circuit also includes a second subsystem including a second clock generator configured to generate a second clock signal. The first subsystem includes an edge detector configured to detect an edge of the second clock signal. The first clock generator generates the first clock signal with a selected phase relative to the second clock signal based on the edge of the second clock signal.

公开(公告)号：US20230101518A1

公开(公告)日：2023-03-30

申请号：US18075977

申请日：2022-12-06

Applicant: STMicroelectronics International N.V.

Inventor： Ankur BAL ,  Vikram SINGH

IPC: H03M1/10 ,  H03M1/06 ,  H03M1/08

Abstract: A time-interleaved analog to digital converter (TI-ADC) includes a first sub-ADC configured to sample and convert an input analog signal to generate a first digital signal and a second sub-ADC configured to sample and convert said input analog signal to generate a second digital signal. Sampling by the second sub-ADC occurs with a time skew mismatch. A multiplexor interleaves the first and second digital signals to generate a third digital signal. A time skew mismatch error determination circuit processes the first and second digital signals to generate a time error corresponding to the time skew mismatch. A slope value of said third digital signal is determined and multiplied by the time error to generate a signal error. The signal error is summed with the third digital signal to generate a digital output signal which eliminates the error due to the time skew mismatch. This correction is performed in real time.

公开(公告)号：US20230062144A1

公开(公告)日：2023-03-02

申请号：US17898239

申请日：2022-08-29

Applicant: STMicroelectronics International N.V.

Inventor： Ankur BAL ,  Namerita KHANNA ,  Rajnish GARG ,  Rohit Kumar GUPTA

IPC: H04L7/033 ,  H03K19/21 ,  H03K3/037

Abstract: A device includes input data lines associated with a first time domain and output data lines associated with a second time domain. Synchronizing circuitry is coupled between the input data lines and output data lines. The synchronizing circuitry is driven by a synchronizing clock signal generated by clock generating circuitry. The clock generating circuitry is coupled to the input data lines and the synchronizing circuitry. In operation, the clock generating circuitry detects signal transitions on the plurality of input data lines. The clock generating circuitry generates the synchronizing clock signal that drives the synchronizing circuitry based on detected transitions, a clock signal of the first time domain, and a clock signal of the second time domain.

公开(公告)号：US20230033569A1

公开(公告)日：2023-02-02

申请号：US17867496

申请日：2022-07-18

Applicant: STMicroelectronics International N.V.

Inventor： Ankur BAL ,  Rupesh SINGH

IPC: H03H17/02

Abstract: A finite impulse response (FIR) filter includes a plurality of registers. The data input terminal of each register is directly coupled to the input of the FIR filter. A new data value is passed to each register on each clock cycle of a filter clock signal. Only one of the registers processes the data value on each clock cycle. A ring counter is coupled to the registers and determines which register processes the data value on each dock cycle.

公开(公告)号：US20220066498A1

公开(公告)日：2022-03-03

申请号：US17393492

申请日：2021-08-04

Applicant: STMicroelectronics International N.V.

Inventor： Ankur BAL ,  Abhishek Kishore KAUL ,  Jeet Narayan TIWARI

IPC: G06F1/04

Abstract: An N-bit linear feedback shift register includes P parallel chains of flip flops each having an input and output. The input is coupled to output of an XOR circuit for that parallel chain. Inputs of the XOR circuit for that parallel chain are coupled to outputs of different flip flops of the P parallel chains according to exponents of a primitive polynomial of order N−1. The flip flops of the P parallel chains of flip flops are clocked by a second clock. At each rising edge of the second clock, P LFSR pre-outputs are respectively produced from the outputs of last flip flops of each of P parallel chains of flip flops. Readout circuitry clocked by a first clock having a frequency that is P times that of the first clock passes a different one of the P pre-LFSR outputs at each clock cycle as a LFSR output.

公开(公告)号：US20220006467A1

公开(公告)日：2022-01-06

申请号：US17342416

申请日：2021-06-08

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Ankur BAL ,  Sri Ram GUPTA ,  Rupesh SINGH

IPC: H03M1/10 ,  H03M1/38

Abstract: An integrated circuit includes a successive approximation register (SAR) analog-to-digital converter (ADC). The ADC includes a bit step selector. During testing of the ADC, the bit step selector selects a number of bits to be tested for a next analog test voltage based on digital values that are within an integer delta value of most recent digital value for a most recent analog test voltage.

公开(公告)号：US20200186162A1

公开(公告)日：2020-06-11

申请号：US16702246

申请日：2019-12-03

Applicant: STMicroelectronics International N.V.

Inventor： Ankur BAL ,  Rupesh SINGH

IPC: H03M3/00 ,  H03K3/037 ,  G06F1/10

Abstract: A continuous time Delta-Sigma (CT-ΔΣ) modulator has an input node configured to receive an input signal and an output node configured to output a digital output signal. The CT-ΔΣ modulator includes a feedback loop with a summation circuit configured to sum the digital output signal with a jitter perturbed test signal to generate a signal supplied to an input of a digital to analog converter circuit. A single tone signal is injected with a jitter error of a clock signal to generate the jitter perturbed test signal. A processing circuit processes the digital output signal to detect a signal to noise ratio of the CT-ΔΣ modulator. The detected signal to noise ratio is indicative of presence of jitter in the clock signal.

公开(公告)号：US20190384347A1

公开(公告)日：2019-12-19

申请号：US16437705

申请日：2019-06-11

Applicant: STMicroelectronics International N.V.

Inventor： Ankur BAL ,  Rupesh SINGH

IPC: G06F1/02 ,  H03K3/80 ,  H03K4/02

Abstract: A recursive digital sinusoid generator generates recursive values used in the production of a digital sinusoid output. The recursive values are generated at a first frequency. A sinusoid value generator generates replacement values at a second frequency, wherein the second frequency is less than the first frequency. The generated recursive values are periodically replaced with the generated replacement values without interrupting production of the digital sinusoid output at the first frequency. This periodic replacement effectively corrects for a finite precision error which accumulates in the recursive values over time.

公开(公告)号：US20240195432A1

公开(公告)日：2024-06-13

申请号：US18521725

申请日：2023-11-28

Applicant: STMicroelectronics International N.V.

Inventor： Ankur BAL ,  Vikram SINGH

IPC: H03M3/00

CPC classification number: H03M3/458 ,  H03H21/0012

Abstract: Various examples in accordance with the present disclosure provide example methods, systems, and apparatuses that may reduce direct current (DC) bias in biased signal inputs.