公开(公告)号：US20140319648A1

公开(公告)日：2014-10-30

申请号：US14261757

申请日：2014-04-25

Applicant: Commissariat a I'energie atomique et aux energies alternatives ,  STMicroelectronics SA

Inventor： Claire Fenouillet-Beranger ,  Pascal Fonteneau

IPC: H01L27/082 ,  H01L27/02

CPC classification number: H01L27/0248 ,  H01L27/0259 ,  H01L27/0296 ,  H01L27/1207

Abstract: An integrated circuit includes first and second electronic components, a buried UTBOX insulating layer, first and second ground planes plumb with the first and second electronic components, first and second wells, first and second biasing electrodes making contact with the first and second wells and with the first and second ground planes, a third electrode making contact with the first well, a first trench isolation separating the first and third electrodes and extending through the buried insulating layer as far as into the first well, and a second trench isolation that isolates the first electrode from the first component, and that does not extend as far as the interface between the first ground plane and the first well.

Abstract translation: 集成电路包括第一和第二电子元件，埋入的UTBOX绝缘层，第一和第二接地平面与第一和第二电子元件铅垂，第一和第二阱，与第一和第二阱接触的第一和第二偏压电极以及与 所述第一和第二接地平面，与所述第一阱接触的第三电极，分隔所述第一和第三电极并延伸穿过所述埋入绝缘层的第一沟槽隔离层，并且延伸到所述第一阱中;以及第二沟槽隔离， 第一电极，并且不延伸到第一接地平面和第一阱之间的界面。

公开(公告)号：US20140017871A1

公开(公告)日：2014-01-16

申请号：US13933396

申请日：2013-07-02

Applicant: STMicroelectronics SA ,  Commissariat a l'energie atomique et aux energies alternatives

Inventor： Claire Fenouillet-Beranger ,  Pascal Fonteneau

IPC: H01L29/66

CPC classification number: H01L29/66234 ,  H01L27/0259 ,  H01L27/0296 ,  H01L27/0688 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/78606

Abstract: An integrated circuit includes a semiconductor substrate, a silicon layer, a buried isolating layer arranged between the substrate and the layer, a bipolar transistor comprising a collector and emitter having a first doping, and a base and a base contact having a second doping, the base forming a junction with the collector and emitter, the collector, emitter, base contact, and the base being coplanar, a well having the second doping and plumb with the collector, emitter, base contact and base, the well separating the collector, emitter and base contact from the substrate, having the second doping and extending between the base contact and base, a isolating trench plumb with the base and extending beyond the layer but without reaching a bottom of the emitter and collector, and another isolating trench arranged between the base contact, collector, and emitter, the trench extending beyond the buried layer into the well.

Abstract translation: 集成电路包括半导体衬底，硅层，布置在衬底和层之间的掩埋隔离层，包括具有第一掺杂的集电极和发射极的双极晶体管，以及具有第二掺杂的基极和基极触点， 基极与集电极和发射极，集电极，发射极，基极接触和基极共面形成结，阱具有第二掺杂和铅与集电极，发射极，基极接触和基极，阱分离集电极，发射极 和基底接触，具有第二掺杂并且在基底接触和基底之间延伸;隔离沟槽铅与基底并延伸超出该层但不到达发射极和集电极的底部;以及另一隔离沟槽， 基极接触，集电极和发射极，沟槽延伸超过掩埋层进入阱。

公开(公告)号：US20180138181A1

公开(公告)日：2018-05-17

申请号：US15868901

申请日：2018-01-11

Applicant: STMICROELECTRONICS SA

Inventor： Hassan El Dirani ,  Yohann Solaro ,  Pascal Fonteneau

IPC: H01L27/108 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  G11C11/409

CPC classification number: H01L27/10802 ,  G11C11/409 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/407 ,  H01L29/7831 ,  H01L29/7841

Abstract: A microelectronic component is capable of being used as a memory cell. The component includes a semiconductor layer resting on an insulating layer and including a doped source region of a first conductivity type, a doped drain region of a second conductivity type, and an intermediate region, non-doped or more lightly doped, with the second conductivity type, than the drain region, the intermediate region including first and second portions respectively extending from the drain region and from the source region. An insulated front gate electrode rests on the first portion. A first back gate electrode and a second back gate electrode are arranged under the insulating layer, respectively opposite the first portion and the second portion.

公开(公告)号：US09478570B2

公开(公告)日：2016-10-25

申请号：US14929077

申请日：2015-10-30

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Jean-Robert Manouvrier ,  Pascal Fonteneau ,  Xavier Montagner

IPC: H01L27/146 ,  H01L29/423

CPC classification number: H01L27/14614 ,  H01L27/14607 ,  H01L27/14612 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14641 ,  H01L27/14643 ,  H01L27/14687 ,  H01L27/14689 ,  H01L29/4236

Abstract: The present disclosure relates to a photodiode comprising: a P-conductivity type substrate region, an electric charge collecting region for collecting electric charges appearing when a rear face of the substrate region receives light, the collecting region comprising an N-conductivity type region formed deep in the substrate region, an N-conductivity type read region formed in the substrate region, and an isolated transfer gate, formed in the substrate region in a deep isolating trench extending opposite a lateral face of the N-conductivity type region, next to the read region, and arranged for receiving a gate voltage to transfer electric charges stored in the collecting region toward the read region.

公开(公告)号：US09391057B2

公开(公告)日：2016-07-12

申请号：US14261757

申请日：2014-04-25

Applicant: Commissariat a l'energie atomique et aux energies alternatives ,  STMicroelectronics SA

Inventor： Claire Fenouillet-Beranger ,  Pascal Fonteneau

IPC: H01L29/74 ,  H01L27/02 ,  H01L27/12

CPC classification number: H01L27/0248 ,  H01L27/0259 ,  H01L27/0296 ,  H01L27/1207

Abstract: An integrated circuit includes first and second electronic components, a buried UTBOX insulating layer, first and second ground planes plumb with the first and second electronic components, first and second wells, first and second biasing electrodes making contact with the first and second wells and with the first and second ground planes, a third electrode making contact with the first well, a first trench isolation separating the first and third electrodes and extending through the buried insulating layer as far as into the first well, and a second trench isolation that isolates the first electrode from the first component, and that does not extend as far as the interface between the first ground plane and the first well.

Abstract translation: 集成电路包括第一和第二电子元件，埋入的UTBOX绝缘层，第一和第二接地平面与第一和第二电子元件铅垂，第一和第二阱，与第一和第二阱接触的第一和第二偏压电极以及与 所述第一和第二接地平面，与所述第一阱接触的第三电极，分隔所述第一和第三电极并延伸穿过所述埋入绝缘层的第一沟槽隔离层，并且延伸到所述第一阱中;以及第二沟槽隔离， 第一电极，并且不延伸到第一接地平面和第一阱之间的界面。

公开(公告)号：US09165908B2

公开(公告)日：2015-10-20

申请号：US13932134

申请日：2013-07-01

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics SA

Inventor： Claire Fenouillet-Beranger ,  Pascal Fonteneau

IPC: H01L21/70 ,  H01L25/07 ,  H01L27/02 ,  H01L27/12

CPC classification number: H01L25/07 ,  H01L27/0262 ,  H01L27/1207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes four electronic components, a buried UTBOX layer under and plumb with the electronic components, and two pairs of oppositely doped ground planes plumb with corresponding components under the layer. A first isolation trench mutually isolates the ground planes from corresponding wells made plumb and in contact with the ground planes and exhibiting the first doping type. Bias electrodes contact respective wells and ground planes. One pair of electrodes is for connecting to a first bias voltage and the other pair is for connecting to a second bias voltage. Also included are a semiconductor substrate exhibiting the first type of doping and a deeply buried well exhibiting the second type of doping. The deeply buried well contacts the other wells and separates them from the substrate. Finally, a control electrode couples to the deeply buried well.

Abstract translation: 集成电路包括四个电子部件，在电子部件下方并且铅垂的埋入的UTBOX层和在层下方具有相应部件的两对相对掺杂的接地平面。 第一隔离沟槽将接地层与相应的铅垂阱相分离并与接地层接触并呈现出第一掺杂型。 偏置电极接触相应的阱和接地层。 一对电极用于连接到第一偏置电压，另一对电极用于连接到第二偏置电压。 还包括呈现第一类掺杂的半导体衬底和呈现第二类掺杂的深埋阱。 深埋的井与其他井接触并将其与基底分离。 最后，控制电极耦合到深埋井。

公开(公告)号：US09012955B2

公开(公告)日：2015-04-21

申请号：US13921436

申请日：2013-06-19

Applicant: STMicroelectronics SA

Inventor： Pascal Fonteneau

IPC: H01L29/749 ,  H01L27/02 ,  H01L27/12

CPC classification number: H01L29/749 ,  H01L27/0262 ,  H01L27/0296 ,  H01L27/1203 ,  H01L27/1207

Abstract: A MOS transistor protected against overvoltages formed in an SOI-type semiconductor layer arranged on an insulating layer itself arranged on a semiconductor substrate including a lateral field-effect control thyristor formed in the substrate at least partly under the MOS transistor, a field-effect turn-on region of the thyristor extending under at least a portion of a main electrode of the MOS transistor and being separated therefrom by said insulating layer, the anode and the cathode of the thyristor being respectively connected to the drain and to the source of the MOS transistor, whereby the thyristor turns on in case of a positive overvoltage between the drain and the source of the MOS transistor.

Abstract translation: 保护在被布置在绝缘层本身上的SOI型半导体层中形成的过电压的MOS晶体管，其本身布置在半导体衬底上，该半导体衬底包括至少部分地在MOS晶体管下方形成在衬底中的横向场效应控制晶闸管，场效应转 所述晶闸管的区域在所述MOS晶体管的主电极的至少一部分的下方延伸并且被所述绝缘层分离，所述晶闸管的阳极和阴极分别连接到所述MOS的漏极和源极 晶体管，由此在MOS晶体管的漏极和源极之间的正过电压的情况下晶闸管导通。

公开(公告)号：US20150086154A1

公开(公告)日：2015-03-26

申请号：US14494647

申请日：2014-09-24

Applicant: STMicroelectronics SA

Inventor： Pascal Fonteneau

IPC: G02B6/122 ,  H01L27/02 ,  H01L25/16

CPC classification number: G02B6/4275 ,  G02B6/122 ,  G02B6/428 ,  G02B2006/12061 ,  H01L23/49827 ,  H01L23/528 ,  H01L23/60 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/167 ,  H01L27/0248 ,  H01L27/0255 ,  H01L27/0259 ,  H01L29/87 ,  H01L2224/16235 ,  H01L2225/06534 ,  H01L2225/06572 ,  H01L2924/10253 ,  H01L2924/1431

Abstract: A device includes integrated circuit chips mounted on one another. At least one component for protecting elements of a second chip is formed in a first chip. The chips may be of the SOI type, with the first chip including a first SOI layer having a first thickness and the second chip including a second SOI layer having a second thickness smaller than the first thickness. The first chip including the component for protecting may include an optical waveguide with the component for protecting formed adjacent the optical waveguide.

Abstract translation: 一种装置包括彼此安装的集成电路芯片。 用于保护第二芯片的元件的至少一个部件形成在第一芯片中。 芯片可以是SOI型，其中第一芯片包括具有第一厚度的第一SOI层，第二芯片包括第二厚度小于第一厚度的第二SOI层。 包括用于保护的部件的第一芯片可以包括具有邻近光波导形成的用于保护的部件的光波导。

公开(公告)号：US20140017858A1

公开(公告)日：2014-01-16

申请号：US13933441

申请日：2013-07-02

Applicant: STMicroelectronics SA ,  Commissariat a l'energie atomique et aux energies alternatives

Inventor： Claire Fenouillet-Beranger ,  Pascal Fonteneau

IPC: H01L27/12

CPC classification number: H01L27/1203 ,  H01L27/0255 ,  H01L27/0296 ,  H01L27/1207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a transistor, an UTBOX buried insulating layer disposed under it, a ground plane disposed under the layer, a well disposed under the plane, a first trench made at a periphery of the transistor and extending through the layer and into the well, a substrate situated under the well, a p-n diode made on a side of the transistor and comprising first and second zones of opposite doping, the first zone being configured for electrical connection to a first electrode of the transistor, wherein first and second zones are coplanar with the plane, a second trench for separating the first and second zones, the second trench extending through the layer into the plane and until a depth less than an interface between the plane and the well, and a third zone under the second trench forming a junction between the zones.

Abstract translation: 集成电路包括晶体管，设置在其下的UTBOX埋入绝缘层，设置在层下面的接地平面，布置在平面下的阱，在晶体管的周围形成并延伸穿过该层并进入阱的第一沟槽 位于阱下的衬底，在晶体管的一侧制成的pn二极管，其包括相反掺杂的第一和第二区，第一区被配置为电连接到晶体管的第一电极，其中第一和第二区是 与所述平面共面的第二沟槽，用于分离所述第一和第二区域的第二沟槽，所述第二沟槽延伸穿过所述层进入所述平面并且直到深度小于所述平面和所述阱之间的界面，以及在所述第二沟槽形成之下的第三区域 区域之间的连接处。

公开(公告)号：US20140017856A1

公开(公告)日：2014-01-16

申请号：US13933379

申请日：2013-07-02

Applicant: STMicroelectronics SA ,  Commissariat à I'ènergie atomique et aux energies alternatives

Inventor： Claire Fenouillet-Beranger ,  Pascal Fonteneau

IPC: H01L29/66

CPC classification number: H01L29/66477 ,  H01L27/0296 ,  H01L27/0688 ,  H01L27/1207

Abstract: An integrated circuit features a FET, an UTBOX layer plumb with the FET, an underlayer ground plane with first doping plumb with the FET's gate and channel, first and second underlayer semiconducting elements, both plumb with the drain or source, electrodes in contact respectively with the ground plane and with the first element, one having first doping and being connected to a first voltage, the other having the first doping and connected to a second bias voltage different from the first, a semiconducting well having the second doping and plumb with the first ground plane and both elements, a first trench isolating the first FET from other components of the integrated circuit and extending through the layer into the well, and second and third trenches isolating the FET from the electrodes, and extending to a depth less than a plane/well interface.

Abstract translation: 集成电路具有FET，具有FET的UTBOX层铅垂，具有FET的栅极和沟道的第一掺杂铅垂的下层接地层，第一和第二下层半导体元件，两者均与漏极或源极接触，电极分别接触 接地平面和第一元件，一个具有第一掺杂并且连接到第一电压，另一个具有第一掺杂并且连接到不同于第一掺杂的第二偏置电压，具有第二掺杂和铅垂的半导体阱与 第一接地平面和两个元件，第一沟槽将第一FET与集成电路的其它部件隔离并延伸穿过该阱进入阱，第二和第三沟槽将FET与电极隔离，并延伸至小于 平面/井界面。