公开(公告)号：US09209211B2

公开(公告)日：2015-12-08

申请号：US14660847

申请日：2015-03-17

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Jean-Robert Manouvrier ,  Pascal Fonteneau ,  Xavier Montagner

IPC: H01L27/146 ,  H01L29/423

CPC classification number: H01L27/14614 ,  H01L27/14607 ,  H01L27/14612 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14641 ,  H01L27/14643 ,  H01L27/14687 ,  H01L27/14689 ,  H01L29/4236

Abstract: The present disclosure relates to a photodiode comprising: a P-conductivity type substrate region, an electric charge collecting region for collecting electric charges appearing when a rear face of the substrate region receives light, the collecting region comprising an N-conductivity type region formed deep in the substrate region, an N-conductivity type read region formed in the substrate region, and an isolated transfer gate, formed in the substrate region in a deep isolating trench extending opposite a lateral face of the N-conductivity type region, next to the read region, and arranged for receiving a gate voltage to transfer electric charges stored in the collecting region toward the read region.

Abstract translation: 本发明涉及一种光电二极管，包括：P导电型衬底区域，用于收集当衬底区域的后表面接收光时出现的电荷的电荷收集区域，所述收集区域包括形成深的N导电类型区域 在基板区域中，形成在基板区域中的N导电型读取区域和隔离的转移栅极，形成在与N导电型区域的侧面相反延伸的深隔离沟槽中的基板区域中， 并且被布置为接收栅极电压以将存储在收集区域中的电荷转移到读取区域。

公开(公告)号：US20140015052A1

公开(公告)日：2014-01-16

申请号：US13932371

申请日：2013-07-01

Applicant: STMicroelectronics SA ,  Commissariat a l'energie atomique et aux energies alternatives

Inventor： Claire Fenouillet-Beranger ,  Pascal Fonteneau

IPC: H01L27/12

CPC classification number: H01L27/1203 ,  H01L27/0262 ,  H01L27/0296 ,  H01L27/0688 ,  H01L27/1207

Abstract: An integrated circuit includes an UTBOX insulating layer under and plumb with first and second electronic components, and corresponding ground planes and oppositely-doped wells made plumb with them. The wells contact with corresponding ground planes. A pair of oppositely doped bias electrodes, suitable for connecting corresponding bias voltages, contacts respective wells and ground planes. A third electrode contacts the first well. A first trench isolates one bias electrode from the third electrode and extends through the layer and into the first well. A second trench isolates the first bias electrode from one component. This trench has an extent that falls short of reaching an interface between the first ground plane and the first well.

Abstract translation: 集成电路包括在第一和第二电子部件下面并且铅垂的UTBOX绝缘层，以及相应的接地平面和与其相反的相对掺杂的阱。 油井与相应的地面接触。 一对相对掺杂的偏置电极适于连接相应的偏置电压，接触相应的阱和接地层。 第三电极接触第一阱。 第一沟槽将一个偏置电极与第三电极隔离并延伸穿过该层并进入第一阱。 第二沟槽将第一偏置电极与一个部件隔离。 该沟槽的程度不足以达到第一接地层与第一井之间的界面。

公开(公告)号：US20180061838A1

公开(公告)日：2018-03-01

申请号：US15464537

申请日：2017-03-21

Applicant: STMicroelectronics SA

Inventor： Hassan El Dirani ,  Yohann Solaro ,  Pascal Fonteneau

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  G11C11/409

CPC classification number: H01L27/10802 ,  G11C11/409 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/407 ,  H01L29/7831 ,  H01L29/7841

Abstract: A microelectronic component is capable of being used as a memory cell. The component includes a semiconductor layer resting on an insulating layer and including a doped source region of a first conductivity type, a doped drain region of a second conductivity type, and an intermediate region, non-doped or more lightly doped, with the second conductivity type, than the drain region, the intermediate region including first and second portions respectively extending from the drain region and from the source region. An insulated front gate electrode rests on the first portion. A first back gate electrode and a second back gate electrode are arranged under the insulating layer, respectively opposite the first portion and the second portion.

公开(公告)号：US09666577B2

公开(公告)日：2017-05-30

申请号：US14450597

申请日：2014-08-04

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics SA ,  Centre National de la Recherche Scientifique

Inventor： Yohann Solaro ,  Sorin Cristoloveanu ,  Claire Fenouillet-Beranger ,  Pascal Fonteneau

IPC: H01L27/02 ,  H01L27/12 ,  H01L29/66 ,  H01L29/747 ,  H01L29/78 ,  H01L29/423 ,  H01L29/74 ,  H01L29/749 ,  H01L29/10

CPC classification number: H01L27/0262 ,  H01L27/1203 ,  H01L29/1012 ,  H01L29/42308 ,  H01L29/66477 ,  H01L29/7436 ,  H01L29/747 ,  H01L29/749 ,  H01L29/78 ,  H01L29/7833

Abstract: The invention relates to an IC with an electrostatic discharge protection device. There is a buried insulant layer 50 nm or less in thickness and first and second bipolar transistors on the insulant layer, one being an npn transistor and the other a pnp transistor. The base of the first transistor is merged with the collector of the second transistor and the base of the second transistor is merged with the collector of the first transistor. The first and second bipolar transistors are configured to selectively conduct a discharge current between two electrodes of the protection device. There is a first semiconductor ground plane under the insulant layer, being electrically biased, extending until it is plumb with the base of the first bipolar transistor, exhibiting a first type of doping identical to that of the base of the first bipolar transistor with a doping density at least ten times greater.

公开(公告)号：US09354391B2

公开(公告)日：2016-05-31

申请号：US14494647

申请日：2014-09-24

Applicant: STMicroelectronics SA

Inventor： Pascal Fonteneau

IPC: G02B6/12 ,  G02B6/122 ,  H01L25/16 ,  H01L27/02 ,  H01L23/60 ,  H01L25/065 ,  H01L23/00

CPC classification number: G02B6/4275 ,  G02B6/122 ,  G02B6/428 ,  G02B2006/12061 ,  H01L23/49827 ,  H01L23/528 ,  H01L23/60 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/167 ,  H01L27/0248 ,  H01L27/0255 ,  H01L27/0259 ,  H01L29/87 ,  H01L2224/16235 ,  H01L2225/06534 ,  H01L2225/06572 ,  H01L2924/10253 ,  H01L2924/1431

Abstract: A device includes integrated circuit chips mounted on one another. At least one component for protecting elements of a second chip is formed in a first chip. The chips may be of the SOI type, with the first chip including a first SOI layer having a first thickness and the second chip including a second SOI layer having a second thickness smaller than the first thickness. The first chip including the component for protecting may include an optical waveguide with the component for protecting formed adjacent the optical waveguide.

Abstract translation: 一种装置包括彼此安装的集成电路芯片。 用于保护第二芯片的元件的至少一个部件形成在第一芯片中。 芯片可以是SOI型，其中第一芯片包括具有第一厚度的第一SOI层，第二芯片包括第二厚度小于第一厚度的第二SOI层。 包括用于保护的部件的第一芯片可以包括具有邻近光波导形成的用于保护的部件的光波导。

公开(公告)号：US20150061023A1

公开(公告)日：2015-03-05

申请号：US14450597

申请日：2014-08-04

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics SA ,  Centre National de la Recherche Scientifique

Inventor： Yohann Solaro ,  Sorin Cristoloveanu ,  Claire Fenouillet-Beranger ,  Pascal Fonteneau

IPC: H01L27/02 ,  H01L29/66 ,  H01L27/12 ,  H01L29/747 ,  H01L29/78

CPC classification number: H01L27/0262 ,  H01L27/1203 ,  H01L29/1012 ,  H01L29/42308 ,  H01L29/66477 ,  H01L29/7436 ,  H01L29/747 ,  H01L29/749 ,  H01L29/78 ,  H01L29/7833

Abstract: The invention relates to an IC with an electrostatic discharge protection device. There is a buried insulant layer 50 nm or less in thickness and first and second bipolar transistors on the insulant layer, one being an npn transistor and the other a pnp transistor. The base of the first transistor is merged with the collector of the second transistor and the base of the second transistor is merged with the collector of the first transistor. The first and second bipolar transistors are configured to selectively conduct a discharge current between two electrodes of the protection device. There is a first semiconductor ground plane under the insulant layer, being electrically biased, extending until it is plumb with the base of the first bipolar transistor, exhibiting a first type of doping identical to that of the base of the first bipolar transistor with a doping density at least ten times greater.

Abstract translation: 本发明涉及具有静电放电保护装置的IC。 在绝缘层上存在厚度为50nm以下的绝缘绝缘层和第一和第二双极晶体管，一个为npn晶体管，另一个为pnp晶体管。 第一晶体管的基极与第二晶体管的集电极合并，第二晶体管的基极与第一晶体管的集电极合并。 第一和第二双极晶体管被配置为选择性地在保护装置的两个电极之间传导放电电流。 在绝缘层下方存在第一半导体接地层，被电偏压，延伸直到其与第一双极晶体管的基极相连，表现出与第一双极晶体管的基极相同的第一类掺杂，掺杂 密度至少十倍以上。

公开(公告)号：US10312240B2

公开(公告)日：2019-06-04

申请号：US15868901

申请日：2018-01-11

Applicant: STMICROELECTRONICS SA

Inventor： Hassan El Dirani ,  Yohann Solaro ,  Pascal Fonteneau

IPC: H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/78 ,  G11C11/409 ,  H01L27/108

Abstract: A microelectronic component is capable of being used as a memory cell. The component includes a semiconductor layer resting on an insulating layer and including a doped source region of a first conductivity type, a doped drain region of a second conductivity type, and an intermediate region, non-doped or more lightly doped, with the second conductivity type, than the drain region, the intermediate region including first and second portions respectively extending from the drain region and from the source region. An insulated front gate electrode rests on the first portion. A first back gate electrode and a second back gate electrode are arranged under the insulating layer, respectively opposite the first portion and the second portion.

公开(公告)号：US10062681B2

公开(公告)日：2018-08-28

申请号：US15591565

申请日：2017-05-10

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics SA ,  Centre National de la Recherche Scientifique

Inventor： Yohann Solaro ,  Sorin Cristoloveanu ,  Claire Fenouillet-Beranger ,  Pascal Fonteneau

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/74 ,  H01L29/749 ,  H01L29/747 ,  H01L29/66 ,  H01L29/423 ,  H01L29/10 ,  H01L27/12

CPC classification number: H01L27/0262 ,  H01L27/1203 ,  H01L29/1012 ,  H01L29/42308 ,  H01L29/66477 ,  H01L29/7436 ,  H01L29/747 ,  H01L29/749 ,  H01L29/78 ,  H01L29/7833

Abstract: A protection device for protecting an IC against electrostatic discharge includes a buried insulant layer having a thickness that is no greater than fifty nanometers with bipolar transistors arranged thereon, one of which is NPN and the other of which is PNP. A base of one merges with a collector of the other. The transistors selectively conduct a discharge current between electrodes. A first semiconductor ground plane under the buried insulant layer is capable of being electrically biased and extends underneath the base of the first bipolar transistor. The ground plane and a base of one transistor have the same doping. However, its dopant density is at least tenfold greater than that of the base.

公开(公告)号：US09653476B2

公开(公告)日：2017-05-16

申请号：US13933441

申请日：2013-07-02

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics SA

Inventor： Claire Fenouillet-Beranger ,  Pascal Fonteneau

IPC: H01L27/12 ,  H01L27/02

CPC classification number: H01L27/1203 ,  H01L27/0255 ,  H01L27/0296 ,  H01L27/1207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a transistor, an UTBOX buried insulating layer disposed under it and a ground plane disposed under the layer. A well is disposed under the plane and a first trench is at the periphery of the transistor and extends through the layer into the well. There is a substrate under the well and a p-n diode on a side of the transistor. The diode comprises first and second zones of opposite doping and the first zone is configured for electrical connection to a first electrode of the transistor. The first and second zones are coplanar with the plane and a second trench for separating the first and second zones. The second trench extends through the layer into the plane to a depth less than an interface between the plane and the well. There is a third zone under the second trench forming a junction between the zones.

公开(公告)号：US09530922B2

公开(公告)日：2016-12-27

申请号：US14496192

申请日：2014-09-25

Applicant: STMICROELECTRONICS SA

Inventor： Pascal Fonteneau

IPC: H01L31/111 ,  H01L31/0232 ,  H01L31/18 ,  H01L31/11 ,  H01L31/02 ,  H01L27/12 ,  H01L31/028 ,  H01L31/105

CPC classification number: H01L31/1113 ,  H01L27/1203 ,  H01L31/02019 ,  H01L31/02327 ,  H01L31/028 ,  H01L31/105 ,  H01L31/11 ,  H01L31/18 ,  Y02E10/547

Abstract: An overvoltage protection component may be in a SOI layer, a portion of the SOI layer forming the core of an optical waveguide. This component may be made of semiconductor regions of different doping types and/or levels, at least one of these regions corresponding to at least a portion of the waveguide core.

Abstract translation: 过电压保护组件可以在SOI层中，SOI层的一部分形成光波导的核心。 该组件可以由不同掺杂类型和/或电平的半导体区域制成，这些区域中的至少一个对应于波导芯的至少一部分。