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公开(公告)号：US11356018B2
公开(公告)日：2022-06-07
申请号：US17313533
申请日：2021-05-06
Applicant: STMicroelectronics International N.V.
Inventor： Vikas Rana
IPC: H02M3/07
Abstract: A charge pump includes an intermediate node capacitively coupled to receive a first clock signal oscillating between a ground and positive supply voltage, the intermediate node generating a first signal oscillating between a first and second voltage. A level shifting circuit shifts the first signal in response to a second clock signal to generate a second signal oscillating between first and third voltages. A CMOS switching circuit includes a first transistor having a source coupled to an input, a second transistor having a source coupled to an output and a gate coupled to receive the second signal. A common drain of the CMOS switching circuit is capacitively coupled to receive the first clock signal. When positively pumping, the first voltage is twice the second voltage and the third voltage is ground. When negatively pumping, the first and third voltages are of opposite polarity and the second voltage is ground.
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公开(公告)号：US10333397B2
公开(公告)日：2019-06-25
申请号：US15652748
申请日：2017-07-18
Applicant: STMicroelectronics International N.V.
Inventor： Vikas Rana , Abhishek Mittal
IPC: H02M3/07
Abstract: A charge pump includes boosting circuits cascade coupled between first and second nodes, wherein each boosting circuit is operable in both a positive voltage boosting mode to positively boost voltage and a negative voltage boosting mode to negatively boost voltage. A first switching circuit selectively applies a first voltage to one of the cascaded boosting circuits in response to a first logic state of a periodic enable signal, with the cascaded boosting circuits operating in the positive voltage boosting mode to produce a high positive voltage at the second node. A second switching circuit selectively applies a second voltage to another of the cascaded boosting circuits in response to a second logic state of the periodic enable signal, with the cascaded boosting circuits operating in the negative voltage boosting mode to produce a high negative voltage at the first node. Simultaneous output of the positive and negative voltages is made.
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公开(公告)号：US10250133B2
公开(公告)日：2019-04-02
申请号：US15652447
申请日：2017-07-18
Applicant: STMicroelectronics International N.V.
Inventor： Vikas Rana
Abstract: A single stage voltage quadrupler circuit includes a first capacitive voltage boosting circuit responsive to a first clock signal and operable to boost a voltage at a first node in response to the first clock signal from a first voltage level to a second voltage level that is substantially two times the first voltage level. A pass transistor selectively passes the boosted voltage at the first node to a second node in response to a control signal generated by a bootstrapping capacitor circuit in response to the level shifted first clock signal. A second capacitive boosting circuit is operable to boost the voltage at the second node in response to a level shifted second clock signal that is the logical invert of the level shifted first clock signal to third voltage level that is substantially four times the first voltage level.
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公开(公告)号：US10176869B2
公开(公告)日：2019-01-08
申请号：US16044280
申请日：2018-07-24
Inventor： Marco Pasotti , Marcella Carissimi , Vikas Rana
Abstract: A method is provided for operating a memory device that includes an array of memory cells coupled to a plurality of bitlines. A memory cell is selected from among the array of memory cells. The selected memory cell is coupled to a selected bitline. During a program operation, a program current pulse is injected into the selected memory cell via a first switch coupled to the bitline. At an end of the program current pulse, the selected bitline is discharged via a second switch coupled to the bitline.
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公开(公告)号：US12148473B2
公开(公告)日：2024-11-19
申请号：US17697846
申请日：2022-03-17
Inventor： Roberto Bregoli , Vikas Rana
Abstract: In an embodiment a non-volatile memory cell includes a substrate, a first body in the substrate, a second body in the substrate, a first storage transistor having a first conduction region and a second conduction region in the first body, the first and second conduction regions delimiting a first channel region in the first body, a first control gate region in the second body, an insulating region overlying the substrate, a single floating gate region extending on the substrate and embedded in the insulating region, the single floating gate region having a first portion on the first body and a second portion on the second body, the first portion and second portion being connected and electrically coupled, a first selection via extending through the insulating region and electrically coupling the first conduction region with a first conduction node, a second selection via extending through the insulating region and electrically coupling the second conduction region with a second conduction node and a first control via extending though the insulating region and electrically coupling the first control gate region with a first control node.
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Patent Agency Ranking
公开(公告)号：US12087368B2
公开(公告)日：2024-09-10
申请号：US17548096
申请日：2021-12-10
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Arpit Vijayvergia , Vikas Rana
CPC classification number: G11C16/28 , G11C16/0458 , G11C16/24
Abstract: An integrated circuit includes a memory array and a memory read circuitry for reading data from the memory array. The memory read circuitry includes a leakage current compensation circuit. The leakage current compensation circuit senses the leakage current in a bitline of the memory array during a read operation and generates a leakage compensation current to offset the leakage current during the read operation.
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公开(公告)号：US11881280B2
公开(公告)日：2024-01-23
申请号：US17534136
申请日：2021-11-23
Applicant: STMicroelectronics International N.V.
Inventor： Shivam Kalla , Vikas Rana
IPC: G05F3/02 , G05F1/10 , G11C5/14 , G11C11/56 , H02M1/00 , H03K5/24 , G05F3/26 , H02M3/07 , G11C16/30
CPC classification number: G11C5/145 , G05F3/262 , G11C5/147 , G11C11/5635 , G11C16/30 , H02M1/0003 , H02M3/07 , H03K5/24
Abstract: An integrated circuit includes a non-volatile memory, a charge pump that generates high voltages for programming operations of the non-volatile memory array, and a charge pump regulator that controls a slew rate of the charge pump. The charge pump regulator generates a sense current indicative of the slew rate and adjusts a frequency of a clock signal provided to the charge pump based on the sense current.
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28.发明申请公开(公告)号：US20220319598A1
公开(公告)日：2022-10-06
申请号：US17697846
申请日：2022-03-17
Inventor： Roberto Bregoli , Vikas Rana
IPC: G11C16/04 , H01L27/11524 , H01L27/1156 , G11C16/10 , G11C16/14 , G11C16/26
Abstract: In an embodiment a non-volatile memory cell includes a substrate, a first body in the substrate, a second body in the substrate, a first storage transistor having a first conduction region and a second conduction region in the first body, the first and second conduction regions delimiting a first channel region in the first body, a first control gate region in the second body, an insulating region overlying the substrate, a single floating gate region extending on the substrate and embedded in the insulating region, the single floating gate region having a first portion on the first body and a second portion on the second body, the first portion and second portion being connected and electrically coupled, a first selection via extending through the insulating region and electrically coupling the first conduction region with a first conduction node, a second selection via extending through the insulating region and electrically coupling the second conduction region with a second conduction node and a first control via extending though the insulating region and electrically coupling the first control gate region with a first control node.
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公开(公告)号：US11205462B2
公开(公告)日：2021-12-21
申请号：US17010704
申请日：2020-09-02
Inventor： Vivek Tyagi , Vikas Rana , Chantal Auricchio , Laura Capecchi
IPC: G11C7/10 , G11C7/12 , G11C7/06 , G11C11/4094 , G11C11/4091 , G11C7/22
Abstract: A read signal generator generates read signals to control read operations of a memory array. The read signal generator can be selectively controlled to generate an oscillating signal having a period that corresponds to a feature one of the read signals. The oscillating signal is passed to a frequency divider that divides the oscillating signal and provides the divided oscillating signal to an output pad. The frequency of the oscillating signal can be measured at the output pad. The frequency of the oscillating signal, and the duration of the read signal feature can be calculated from the frequency of the oscillating signal. The read signal feature can then be adjusted if needed.
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30.发明授权公开(公告)号：US11183924B2
公开(公告)日：2021-11-23
申请号：US17021013
申请日：2020-09-15
Applicant: STMicroelectronics International N.V.
Inventor： Vikas Rana
IPC: H02M3/07 , H03K19/096 , G05F1/10
Abstract: A voltage doubler circuit supports operation in both a positive voltage boosting mode to positively boost voltage from a first node to a second node and a negative voltage boosting mode to negatively boost voltage from the second node to the first node. The voltage doubler circuit is formed by transistors of a same conductivity type that share a common bulk that is not tied to a source of any of the voltage doubler circuit transistors. A bias generator circuit is coupled to receive a first voltage from the first node and second voltage from the second node. The bias generator circuit operates to apply a lower one of the first and second voltages to the common bulk.
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