公开(公告)号：US09165943B2

公开(公告)日：2015-10-20

申请号：US13932371

申请日：2013-07-01

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics SA

Inventor： Claire Fenouillet-Beranger ,  Pascal Fonteneau

IPC: H01L27/12 ,  H01L27/02 ,  H01L27/06

CPC classification number: H01L27/1203 ,  H01L27/0262 ,  H01L27/0296 ,  H01L27/0688 ,  H01L27/1207

Abstract: An integrated circuit includes an UTBOX insulating layer under and plumb with first and second electronic components, and corresponding ground planes and oppositely-doped wells made plumb with them. The wells contact with corresponding ground planes. A pair of oppositely doped bias electrodes, suitable for connecting corresponding bias voltages, contacts respective wells and ground planes. A third electrode contacts the first well. A first trench isolates one bias electrode from the third electrode and extends through the layer and into the first well. A second trench isolates the first bias electrode from one component. This trench has an extent that falls short of reaching an interface between the first ground plane and the first well.

Abstract translation: 集成电路包括在第一和第二电子部件下面并且铅垂的UTBOX绝缘层，以及相应的接地平面和与其相反的相对掺杂的阱。 油井与相应的地面接触。 一对相对掺杂的偏置电极适于连接相应的偏置电压，接触相应的阱和接地层。 第三电极接触第一阱。 第一沟槽将一个偏置电极与第三电极隔离并延伸穿过该层并进入第一阱。 第二沟槽将第一偏置电极与一个部件隔离。 该沟槽的程度不足以达到第一接地层与第一井之间的界面。

公开(公告)号：US09905565B1

公开(公告)日：2018-02-27

申请号：US15464537

申请日：2017-03-21

Applicant: STMicroelectronics SA

Inventor： Hassan El Dirani ,  Yohann Solaro ,  Pascal Fonteneau

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  G11C11/409

CPC classification number: H01L27/10802 ,  G11C11/409 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/407 ,  H01L29/7831 ,  H01L29/7841

Abstract: A microelectronic component is capable of being used as a memory cell. The component includes a semiconductor layer resting on an insulating layer and including a doped source region of a first conductivity type, a doped drain region of a second conductivity type, and an intermediate region, non-doped or more lightly doped, with the second conductivity type, than the drain region, the intermediate region including first and second portions respectively extending from the drain region and from the source region. An insulated front gate electrode rests on the first portion. A first back gate electrode and a second back gate electrode are arranged under the insulating layer, respectively opposite the first portion and the second portion.

公开(公告)号：US09453977B2

公开(公告)日：2016-09-27

申请号：US15140701

申请日：2016-04-28

Applicant: STMicroelectronics SA

Inventor： Pascal Fonteneau

IPC: G02B6/12 ,  G02B6/42 ,  G02B6/122 ,  H01L23/528 ,  H01L25/16 ,  H01L27/02 ,  H01L29/87 ,  H01L23/498

CPC classification number: G02B6/4275 ,  G02B6/122 ,  G02B6/428 ,  G02B2006/12061 ,  H01L23/49827 ,  H01L23/528 ,  H01L23/60 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/167 ,  H01L27/0248 ,  H01L27/0255 ,  H01L27/0259 ,  H01L29/87 ,  H01L2224/16235 ,  H01L2225/06534 ,  H01L2225/06572 ,  H01L2924/10253 ,  H01L2924/1431

Abstract: A device includes integrated circuit chips mounted on one another. At least one component for protecting elements of a first one of the chips is formed in a second one of the chips. Preferably, the chips are of SOI type, the second chip includes an SOI layer having a first thickness sufficient to support the component for protecting elements. The first chip also includes an SOI layer but having a second thickness smaller than the first thickness that is insufficient to support the component for protecting elements. The SOI layer of the second chip may be an optical waveguide layer.

Abstract translation: 一种装置包括彼此安装的集成电路芯片。 用于保护芯片中的第一芯片的元件的至少一个部件形成在第二芯片中。 优选地，芯片是SOI型的，第二芯片包括具有足以支撑用于保护元件的部件的第一厚度的SOI层。 第一芯片还包括SOI层，但是具有小于不足以支撑用于保护元件的部件的第一厚度的第二厚度。 第二芯片的SOI层可以是光波导层。

公开(公告)号：US09029955B2

公开(公告)日：2015-05-12

申请号：US13933396

申请日：2013-07-02

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics SA

Inventor： Claire Fenouillet-Beranger ,  Pascal Fonteneau

IPC: H01L29/66 ,  H01L27/02 ,  H01L27/06 ,  H01L29/786 ,  H01L27/12 ,  H01L29/732 ,  H01L29/06

CPC classification number: H01L29/66234 ,  H01L27/0259 ,  H01L27/0296 ,  H01L27/0688 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/78606

Abstract: An integrated circuit includes a semiconductor substrate, a silicon layer, a buried isolating layer arranged between the substrate and the layer, a bipolar transistor comprising a collector and emitter having a first doping, and a base and a base contact having a second doping, the base forming a junction with the collector and emitter, the collector, emitter, base contact, and the base being coplanar, a well having the second doping and plumb with the collector, emitter, base contact and base, the well separating the collector, emitter and base contact from the substrate, having the second doping and extending between the base contact and base, a isolating trench plumb with the base and extending beyond the layer but without reaching a bottom of the emitter and collector, and another isolating trench arranged between the base contact, collector, and emitter, the trench extending beyond the buried layer into the well.

Abstract translation: 集成电路包括半导体衬底，硅层，布置在衬底和层之间的掩埋隔离层，包括具有第一掺杂的集电极和发射极的双极晶体管，以及具有第二掺杂的基极和基极触点， 基极与集电极和发射极，集电极，发射极，基极接触和基极共面形成结，阱具有第二掺杂和铅与集电极，发射极，基极接触和基极，阱分离集电极，发射极 和基底接触，具有第二掺杂并且在基底接触和基底之间延伸;隔离沟槽铅与基底并延伸超出该层但不到达发射极和集电极的底部;以及另一隔离沟槽， 基极接触，集电极和发射极，沟槽延伸超过掩埋层进入阱。

公开(公告)号：US20140319648A1

公开(公告)日：2014-10-30

申请号：US14261757

申请日：2014-04-25

Applicant: Commissariat a I'energie atomique et aux energies alternatives ,  STMicroelectronics SA

Inventor： Claire Fenouillet-Beranger ,  Pascal Fonteneau

IPC: H01L27/082 ,  H01L27/02

CPC classification number: H01L27/0248 ,  H01L27/0259 ,  H01L27/0296 ,  H01L27/1207

Abstract: An integrated circuit includes first and second electronic components, a buried UTBOX insulating layer, first and second ground planes plumb with the first and second electronic components, first and second wells, first and second biasing electrodes making contact with the first and second wells and with the first and second ground planes, a third electrode making contact with the first well, a first trench isolation separating the first and third electrodes and extending through the buried insulating layer as far as into the first well, and a second trench isolation that isolates the first electrode from the first component, and that does not extend as far as the interface between the first ground plane and the first well.

Abstract translation: 集成电路包括第一和第二电子元件，埋入的UTBOX绝缘层，第一和第二接地平面与第一和第二电子元件铅垂，第一和第二阱，与第一和第二阱接触的第一和第二偏压电极以及与 所述第一和第二接地平面，与所述第一阱接触的第三电极，分隔所述第一和第三电极并延伸穿过所述埋入绝缘层的第一沟槽隔离层，并且延伸到所述第一阱中;以及第二沟槽隔离， 第一电极，并且不延伸到第一接地平面和第一阱之间的界面。

公开(公告)号：US20140017871A1

公开(公告)日：2014-01-16

申请号：US13933396

申请日：2013-07-02

Applicant: STMicroelectronics SA ,  Commissariat a l'energie atomique et aux energies alternatives

Inventor： Claire Fenouillet-Beranger ,  Pascal Fonteneau

IPC: H01L29/66

CPC classification number: H01L29/66234 ,  H01L27/0259 ,  H01L27/0296 ,  H01L27/0688 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/78606

Abstract: An integrated circuit includes a semiconductor substrate, a silicon layer, a buried isolating layer arranged between the substrate and the layer, a bipolar transistor comprising a collector and emitter having a first doping, and a base and a base contact having a second doping, the base forming a junction with the collector and emitter, the collector, emitter, base contact, and the base being coplanar, a well having the second doping and plumb with the collector, emitter, base contact and base, the well separating the collector, emitter and base contact from the substrate, having the second doping and extending between the base contact and base, a isolating trench plumb with the base and extending beyond the layer but without reaching a bottom of the emitter and collector, and another isolating trench arranged between the base contact, collector, and emitter, the trench extending beyond the buried layer into the well.

Abstract translation: 集成电路包括半导体衬底，硅层，布置在衬底和层之间的掩埋隔离层，包括具有第一掺杂的集电极和发射极的双极晶体管，以及具有第二掺杂的基极和基极触点， 基极与集电极和发射极，集电极，发射极，基极接触和基极共面形成结，阱具有第二掺杂和铅与集电极，发射极，基极接触和基极，阱分离集电极，发射极 和基底接触，具有第二掺杂并且在基底接触和基底之间延伸;隔离沟槽铅与基底并延伸超出该层但不到达发射极和集电极的底部;以及另一隔离沟槽， 基极接触，集电极和发射极，沟槽延伸超过掩埋层进入阱。

公开(公告)号：US20180138181A1

公开(公告)日：2018-05-17

申请号：US15868901

申请日：2018-01-11

Applicant: STMICROELECTRONICS SA

Inventor： Hassan El Dirani ,  Yohann Solaro ,  Pascal Fonteneau

IPC: H01L27/108 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  G11C11/409

CPC classification number: H01L27/10802 ,  G11C11/409 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/407 ,  H01L29/7831 ,  H01L29/7841

Abstract: A microelectronic component is capable of being used as a memory cell. The component includes a semiconductor layer resting on an insulating layer and including a doped source region of a first conductivity type, a doped drain region of a second conductivity type, and an intermediate region, non-doped or more lightly doped, with the second conductivity type, than the drain region, the intermediate region including first and second portions respectively extending from the drain region and from the source region. An insulated front gate electrode rests on the first portion. A first back gate electrode and a second back gate electrode are arranged under the insulating layer, respectively opposite the first portion and the second portion.

公开(公告)号：US09391057B2

公开(公告)日：2016-07-12

申请号：US14261757

申请日：2014-04-25

Applicant: Commissariat a l'energie atomique et aux energies alternatives ,  STMicroelectronics SA

Inventor： Claire Fenouillet-Beranger ,  Pascal Fonteneau

IPC: H01L29/74 ,  H01L27/02 ,  H01L27/12

CPC classification number: H01L27/0248 ,  H01L27/0259 ,  H01L27/0296 ,  H01L27/1207

Abstract: An integrated circuit includes first and second electronic components, a buried UTBOX insulating layer, first and second ground planes plumb with the first and second electronic components, first and second wells, first and second biasing electrodes making contact with the first and second wells and with the first and second ground planes, a third electrode making contact with the first well, a first trench isolation separating the first and third electrodes and extending through the buried insulating layer as far as into the first well, and a second trench isolation that isolates the first electrode from the first component, and that does not extend as far as the interface between the first ground plane and the first well.

Abstract translation: 集成电路包括第一和第二电子元件，埋入的UTBOX绝缘层，第一和第二接地平面与第一和第二电子元件铅垂，第一和第二阱，与第一和第二阱接触的第一和第二偏压电极以及与 所述第一和第二接地平面，与所述第一阱接触的第三电极，分隔所述第一和第三电极并延伸穿过所述埋入绝缘层的第一沟槽隔离层，并且延伸到所述第一阱中;以及第二沟槽隔离， 第一电极，并且不延伸到第一接地平面和第一阱之间的界面。

公开(公告)号：US09165908B2

公开(公告)日：2015-10-20

申请号：US13932134

申请日：2013-07-01

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics SA

Inventor： Claire Fenouillet-Beranger ,  Pascal Fonteneau

IPC: H01L21/70 ,  H01L25/07 ,  H01L27/02 ,  H01L27/12

CPC classification number: H01L25/07 ,  H01L27/0262 ,  H01L27/1207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes four electronic components, a buried UTBOX layer under and plumb with the electronic components, and two pairs of oppositely doped ground planes plumb with corresponding components under the layer. A first isolation trench mutually isolates the ground planes from corresponding wells made plumb and in contact with the ground planes and exhibiting the first doping type. Bias electrodes contact respective wells and ground planes. One pair of electrodes is for connecting to a first bias voltage and the other pair is for connecting to a second bias voltage. Also included are a semiconductor substrate exhibiting the first type of doping and a deeply buried well exhibiting the second type of doping. The deeply buried well contacts the other wells and separates them from the substrate. Finally, a control electrode couples to the deeply buried well.

Abstract translation: 集成电路包括四个电子部件，在电子部件下方并且铅垂的埋入的UTBOX层和在层下方具有相应部件的两对相对掺杂的接地平面。 第一隔离沟槽将接地层与相应的铅垂阱相分离并与接地层接触并呈现出第一掺杂型。 偏置电极接触相应的阱和接地层。 一对电极用于连接到第一偏置电压，另一对电极用于连接到第二偏置电压。 还包括呈现第一类掺杂的半导体衬底和呈现第二类掺杂的深埋阱。 深埋的井与其他井接触并将其与基底分离。 最后，控制电极耦合到深埋井。

公开(公告)号：US09012955B2

公开(公告)日：2015-04-21

申请号：US13921436

申请日：2013-06-19

Applicant: STMicroelectronics SA

Inventor： Pascal Fonteneau

IPC: H01L29/749 ,  H01L27/02 ,  H01L27/12

CPC classification number: H01L29/749 ,  H01L27/0262 ,  H01L27/0296 ,  H01L27/1203 ,  H01L27/1207

Abstract: A MOS transistor protected against overvoltages formed in an SOI-type semiconductor layer arranged on an insulating layer itself arranged on a semiconductor substrate including a lateral field-effect control thyristor formed in the substrate at least partly under the MOS transistor, a field-effect turn-on region of the thyristor extending under at least a portion of a main electrode of the MOS transistor and being separated therefrom by said insulating layer, the anode and the cathode of the thyristor being respectively connected to the drain and to the source of the MOS transistor, whereby the thyristor turns on in case of a positive overvoltage between the drain and the source of the MOS transistor.

Abstract translation: 保护在被布置在绝缘层本身上的SOI型半导体层中形成的过电压的MOS晶体管，其本身布置在半导体衬底上，该半导体衬底包括至少部分地在MOS晶体管下方形成在衬底中的横向场效应控制晶闸管，场效应转 所述晶闸管的区域在所述MOS晶体管的主电极的至少一部分的下方延伸并且被所述绝缘层分离，所述晶闸管的阳极和阴极分别连接到所述MOS的漏极和源极 晶体管，由此在MOS晶体管的漏极和源极之间的正过电压的情况下晶闸管导通。