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公开(公告)号：US20240081099A1
公开(公告)日：2024-03-07
申请号：US18505778
申请日：2023-11-09
Applicant: Samsung Display Co., Ltd.
Inventor： Joon Woo BAE , So Young KOO , Han Bit KIM , Thanh Tien NGUYEN , Kyoung Won LEE , Yong Su LEE , Jae Seob LEE , Gyoo Chul JO
IPC: H10K59/121 , H10K50/844 , H10K59/126 , H10K59/131
CPC classification number: H10K59/1213 , H10K50/844 , H10K59/1216 , H10K59/126 , H10K59/131 , H01L29/7869
Abstract: An organic light emitting diode display according to an exemplary embodiment includes: a substrate; a first buffer layer on the substrate; a first semiconductor layer on the first buffer layer; a first gate insulating layer on the first semiconductor layer; a first gate electrode and a blocking layer on the first gate insulating layer; a second buffer layer on the first gate electrode; a second semiconductor layer on the second buffer layer; a second gate insulating layer on the second semiconductor layer; and a second gate electrode on the second gate insulating layer.
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公开(公告)号：US20240030235A1
公开(公告)日：2024-01-25
申请号：US18480494
申请日：2023-10-03
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： So Young KOO , Jay Bum KIM , Kyung Jin JEON , Eok Su KIM , Jun Hyung LIM
CPC classification number: H01L27/124 , H01L27/1288 , H01L33/62 , H01L2933/0066
Abstract: A display device according to an embodiment of the present disclosure includes: a substrate; a first conductive layer on the substrate; a first insulating layer on the first conductive layer; an active pattern on the first insulating layer and including a semiconductor material; a second insulating layer on the active pattern; and a second conductive layer on the second insulating layer, wherein the first insulating layer has a first opening exposing the first conductive layer, the second insulating layer has a second opening exposing the first conductive layer, a breadth of the first opening is different than a breadth of the second opening, and a side surface of the first opening and a side surface of the second opening are formed to a top surface of the first conductive layer.
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公开(公告)号：US20210249443A1
公开(公告)日：2021-08-12
申请号：US17109601
申请日：2020-12-02
Applicant: Samsung Display Co., Ltd.
Inventor： Kyung Jin JEON , So Young KOO , Eok Su KIM , Hyung Jun KIM , Joon Seok PARK , Jun Hyung LIM
IPC: H01L27/12
Abstract: A display device includes: a substrate; a first conductive layer on the substrate and comprising a first signal line; an insulating layer pattern on the first conductive layer; a semiconductor pattern on the insulating layer pattern; a gate insulating layer on the semiconductor pattern; and a second conductive layer comprising a gate electrode on the gate insulting layer and a first source/drain electrode and a second source/drain electrode, each on at least a part of the semiconductor pattern, wherein the insulating layer pattern and the semiconductor pattern have a same planar shape, the semiconductor pattern comprises a channel region overlapping the gate electrode, a first source/drain region on a first side of the channel region and a second source/drain region on a second side of the channel region, and the first source/drain electrode electrically connects the first source/drain region and the first signal line.
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公开(公告)号：US20210225878A1
公开(公告)日：2021-07-22
申请号：US17085976
申请日：2020-10-30
Applicant: Samsung Display Co., Ltd.
Inventor： So Young KOO , Jay Bum KIM , Kyung Jin JEON , Eok Su KIM , Jun Hyung LIM
Abstract: A display device according to an embodiment of the present disclosure includes: a substrate; a first conductive layer on the substrate; a first insulating layer on the first conductive layer; an active pattern on the first insulating layer and including a semiconductor material; a second insulating layer on the active pattern; and a second conductive layer on the second insulating layer, wherein the first insulating layer has a first opening exposing the first conductive layer, the second insulating layer has a second opening exposing the first conductive layer, a breadth of the first opening is different than a breadth of the second opening, and a side surface of the first opening and a side surface of the second opening are formed to a top surface of the first conductive layer.
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公开(公告)号：US20160365368A1
公开(公告)日：2016-12-15
申请号：US14963769
申请日：2015-12-09
Applicant: Samsung Display Co., Ltd.
Inventor： Masataka KANO , Ji Hun LIM , Yeon Keon MOON , Jun Hyung LIM , So Young KOO , Myoung Hwa KIM
IPC: H01L27/12 , H01L29/788 , H01L29/786 , H01L29/66 , H01L29/417 , H01L29/423
CPC classification number: H01L27/1248 , H01L27/124 , H01L27/1259 , H01L29/41733 , H01L29/42384 , H01L29/4908 , H01L29/66742 , H01L29/66969 , H01L29/78606 , H01L29/78648 , H01L29/7869 , H01L29/788
Abstract: A thin-film transistor array panel includes a substrate, a first gate electrode disposed on the substrate, a first self-assembled monolayer disposed on the first gate electrode, a gate insulating layer disposed on the first self-assembled monolayer, a semiconductor disposed on the gate insulating layer, a drain electrode overlapping the semiconductor, the drain electrode being separated from and facing a source electrode with respect to the semiconductor, a first interlayer insulating layer disposed on the source electrode and the drain electrode, a second self-assembled monolayer disposed on the first interlayer insulating layer, a second gate electrode disposed on the second self-assembled monolayer, a second interlayer insulating layer disposed on the second gate electrode, and a pixel electrode disposed on the second interlayer insulating layer and connected to the drain electrode.
Abstract translation: 薄膜晶体管阵列面板包括基板，设置在基板上的第一栅极电极，设置在第一栅电极上的第一自组装单层，设置在第一自组装单层上的栅极绝缘层，设置在第一自组装单层上的半导体 所述栅极绝缘层，与所述半导体重叠的漏电极，所述漏电极相对于所述半导体分离并面对源电极，设置在所述源电极和所述漏电极上的第一层间绝缘层，第二自组装单层 设置在第一层间绝缘层上的第二栅电极，设置在第二自组装单层上的第二栅电极，设置在第二栅电极上的第二层间绝缘层，以及设置在第二层间绝缘层上并连接到漏极的像素电极 。
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Patent Agency Ranking
公开(公告)号：US20240128251A1
公开(公告)日：2024-04-18
申请号：US18395966
申请日：2023-12-26
Applicant: Samsung Display Co., LTD.
Inventor： Kyung Jin JEON , So Young KOO , Eok Su KIM , Hyung Jun KIM , Yun Yong NAM , Jun Hyung LIM
CPC classification number: H01L25/167 , H01L27/124 , H01L27/1259
Abstract: A display device includes a first conductive layer disposed on a substrate, a passivation layer disposed on the first conductive layer, a second conductive layer disposed on the passivation layer, a via layer disposed on the second conductive layer, a third conductive layer disposed on the via layer, the third conductive layer including a first electrode, a second electrode, a connection pattern, the first electrode, the second electrode, and the connection pattern being spaced apart from each other, and a light emitting element, a first end and a second end of the light emitting element being disposed on the first electrode and the second electrode, respectively, wherein the connection pattern electrically connects the first conductive layer and the second conductive layer through a first contact hole penetrating the via layer and the passivation layer.
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公开(公告)号：US20240121983A1
公开(公告)日：2024-04-11
申请号：US18368461
申请日：2023-09-14
Applicant: Samsung Display Co., LTD.
Inventor： So Young KOO , Myoung Hwa KIM , Eok Su KIM , Hyung Jun Kim
IPC: H10K59/121 , H10K59/12 , H10K59/126 , H10K59/131
CPC classification number: H10K59/1213 , H10K59/1201 , H10K59/1216 , H10K59/126 , H10K59/131
Abstract: A thin film transistor includes a substrate; an active layer including a channel area, a first conductive area, and a second conductive area; a gate insulating layer on a portion of the active layer; a first through hole penetrating through a portion of the first conductive area; a second through hole penetrating through a portion of the second conductive area; a gate electrode overlapping the channel area of the active layer; a first electrode electrically connected to the first conductive area; and a second electrode electrically connected to the second conductive area. One side of the first electrode adjacent to the first through hole is parallel to the one side of the first through hole, the first electrode including protrusion parts at both ends thereof and a groove part concavely recessed from the gate electrode.
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公开(公告)号：US20240040870A1
公开(公告)日：2024-02-01
申请号：US18230281
申请日：2023-08-04
Applicant: Samsung Display Co., LTD.
Inventor： Kyung Jin JEON , So Young KOO , Eok Su KIM , Hyung Jun KIM , Jun Hyung LIM
IPC: H10K59/131 , H10K59/122
CPC classification number: H10K59/131 , H10K59/122 , H10K59/1201
Abstract: A display device includes a substrate, a first conductive layer on the substrate and including a lower light blocking pattern and a first signal line, a buffer layer on the first conductive layer, a semiconductor layer on the buffer layer and including a first semiconductor pattern and a second semiconductor pattern separated from the first semiconductor pattern, an insulating layer on the semiconductor layer and including an insulating layer pattern, a second conductive layer on the insulating layer and including a second signal line, a planarization layer on the second conductive layer, and a third conductive layer on the planarization layer and including an anode electrode. The first semiconductor pattern is electrically connected to the lower light blocking pattern by the anode electrode, and at least a portion of the second semiconductor pattern is isolated from and overlaps each of the first signal line and the second signal line.
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公开(公告)号：US20230253415A1
公开(公告)日：2023-08-10
申请号：US18193200
申请日：2023-03-30
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Kyung Jin JEON , So Young KOO , Eok Su KIM , Hyung Jun KIM , Joon Seok PARK , Jun Hyung LIM
IPC: H01L27/12
CPC classification number: H01L27/124 , H01L27/1262 , H10K59/131
Abstract: A display device includes: a substrate; a first conductive layer on the substrate and comprising a first signal line; an insulating layer pattern on the first conductive layer; a semiconductor pattern on the insulating layer pattern; a gate insulating layer on the semiconductor pattern; and a second conductive layer comprising a gate electrode on the gate insulting layer and a first source/drain electrode and a second source/drain electrode, each on at least a part of the semiconductor pattern, wherein the insulating layer pattern and the semiconductor pattern have a same planar shape, the semiconductor pattern comprises a channel region overlapping the gate electrode, a first source/drain region on a first side of the channel region and a second source/drain region on a second side of the channel region, and the first source/drain electrode electrically connects the first source/drain region and the first signal line.
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公开(公告)号：US20230189585A1
公开(公告)日：2023-06-15
申请号：US17943133
申请日：2022-09-12
Applicant: Samsung Display Co., Ltd.
Inventor： Yun Yong NAM , So Young KOO , Eok Su KIM , Hyung Jun KIM , Jun Hyung LIM , Kyung Jin JEON
CPC classification number: H01L27/3276 , H01L51/56 , H01L51/5253 , H01L51/524 , H01L27/3246 , H01L27/3272
Abstract: The present disclosure relates to a display panel and a method for fabricating the same. According to an embodiment, a method for fabricating a display panel, comprises disposing a circuit array and connection lines on the support substrate, the circuit array disposed in the display area, the connection lines disposed in a non-display area; disposing a via layer on the support substrate; providing a sealing hole surrounding the display area by patterning the via layer; disposing a sealing member surrounding the display area on an encapsulation substrate. In the disposing of the circuit array and the connection lines comprises disposing an active layer overlapping a light shielding member and disposing an etch stopper corresponding to at least a portion of an overlapping area between the sealing hole and the first connecting line part, by patterning a semiconductor material layer on the buffer layer.
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