公开(公告)号：US20190279920A1

公开(公告)日：2019-09-12

申请号：US16426612

申请日：2019-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Wan Kim ,  Jung-Hoon Han ,  Dong-Sik Park

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/538

Abstract: The semiconductor device includes a substrate including an integrated circuit and a contact that are electrically connected to each other, an insulation layer covering the substrate and including metal lines, and a through electrode electrically connected to the integrated circuit. The insulation layer includes an interlayer dielectric layer on the substrate and an intermetal dielectric layer on the interlayer dielectric layer. The metal lines include a first metal line in the interlayer dielectric layer and electrically connected to the contact, and a plurality of second metal lines in the intermetal dielectric layer and electrically connected to the first metal line and the through electrode. The through electrode includes a top surface higher than a top surface of the contact.

公开(公告)号：US09935111B2

公开(公告)日：2018-04-03

申请号：US15631105

申请日：2017-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunjung Kim ,  Sohyun Park ,  Bong-Soo Kim ,  Yoosang Hwang ,  Dong-Wan Kim ,  Junghoon Han

IPC: H01L21/20 ,  H01L27/108

CPC classification number: H01L27/10894 ,  H01L21/0274 ,  H01L21/31051 ,  H01L21/31144 ,  H01L21/565 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10897 ,  H01L27/11582 ,  H01L28/00 ,  H01L28/60

Abstract: A method of forming a semiconductor device includes forming a molding layer and a supporter layer on a substrate including an etch stop layer, forming a mask layer on the supporter layer, forming a first edge blocking layer on the mask layer, forming a mask pattern by etching the mask layer, forming a hole, forming a lower electrode in the hole, forming a supporter mask layer on the supporter layer, forming a second edge blocking layer on the supporter mask layer, forming a supporter mask pattern by patterning the supporter mask layer, forming a supporter opening passing through the supporter layer, removing the molding layer, forming a capacitor dielectric layer and an upper electrode on the lower electrode, forming an interlayer insulating layer on the upper electrode, and planarizing the interlayer insulating layer. The hole passes through the supporter layer, the molding layer and the etch stop layer.

公开(公告)号：US20170256476A1

公开(公告)日：2017-09-07

申请号：US15443259

申请日：2017-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Wan Kim ,  Jung-Hoon HAN ,  Dong-Sik PARK

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/538

CPC classification number: H01L23/481 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/7684 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/5384 ,  H01L2224/11 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: The semiconductor device includes a substrate including an integrated circuit and a contact that are electrically connected to each other, an insulation layer covering the substrate and including metal lines, and a through electrode electrically connected to the integrated circuit. The insulation layer includes an interlayer dielectric layer on the substrate and an intermetal dielectric layer on the interlayer dielectric layer. The metal lines include a first metal line in the interlayer dielectric layer and electrically connected to the contact, and a plurality of second metal lines in the intermetal dielectric layer and electrically connected to the first metal line and the through electrode. The through electrode includes a top surface higher than a top surface of the contact.