公开(公告)号：US10553574B2

公开(公告)日：2020-02-04

申请号：US15298586

申请日：2016-10-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Woo Seo ,  Jin Tae Kim ,  Tae Joong Song ,  Hyoung-Suk Oh ,  Keun Ho Lee ,  Dal Hee Lee ,  Sung We Cho

IPC: H01L27/02 ,  H01L21/8234 ,  H01L23/528 ,  H01L21/67 ,  H01L23/522 ,  H01L27/088 ,  H03K19/177 ,  H03K19/00 ,  H03K19/20 ,  H03K19/21

Abstract: An integrated circuit including a first standard cell including, first transistors, the first transistors being first unfolded transistors, a first metal pin, a second metal pin, and a third metal pin on a first layer, the first metal pin and the second metal pin having a first minimum metal center-to-metal center pitch therebetween less than or equal to 80 nm, a fourth metal pin and a fifth metal pin at a second layer, the fourth metal pin and the fifth metal pin extending in a second direction, the second direction being perpendicular to the first direction, a first via between the first metal pin and the fourth metal pin, and a second via between the third metal pin and the fifth metal pin such that a first via center-to-via center space between the first via and the second via is greater than double the first minimum metal center-to-metal center pitch.

公开(公告)号：US10511293B2

公开(公告)日：2019-12-17

申请号：US16103233

申请日：2018-08-14

Applicant: Samsung Electronics Co., Ltd. ,  KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Jae-Woo Seo ,  Youngsoo Shin ,  Jinwook Jung

IPC: H03K3/3562 ,  H03K3/037 ,  G01R31/317 ,  H01L27/02 ,  G01R31/3185

Abstract: A semiconductor device may include a clock driver including a first gate line, a second gate line, a third gate line and a fourth gate line each extending in a first direction, the first gate line and the second gate line each configured to receive a clock signal, and the third gate line and the fourth gate line each configured to receive an inverted clock signal; a master latch circuit overlapping the first gate line and the third gate line such that the master latch circuit receive the clock signal from the first gate line and receive the inverted clock signal from the third gate line; and a slave latch circuit overlapping the second gate line and the fourth gate line such that the slave latch circuit receives the clock signal from the second gate line, and receives the inverted clock signal from the fourth gate line.

公开(公告)号：US10482082B2

公开(公告)日：2019-11-19

申请号：US14932432

申请日：2015-11-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Woo Seo ,  Yu-Na Kim ,  Ho-Jung Lee ,  Hyuk Kang ,  Ga-Jin Song ,  Jae-Bong Chun ,  Gyu-Cheol Choi ,  Sung-Hyuk Shin ,  Myung-Gon Hong

IPC: G06F16/242 ,  G06F16/28 ,  G06F16/9535 ,  G06F21/62 ,  G06F16/903

Abstract: An electronic device is provided. The electronic device includes a memory configured to store information associated with a user, and a query managing module that is functionally connected with the memory wherein the query managing module is configured to execute acquiring a query, determining at least one word associated with the user, from the query, obtaining a result of a first search executed, based on the at least one word, from a set of protected data associated with the user, changing at least a part of the query, based on the result of the first search, and providing a result of a second search executed, based on the changed query, from a set of public data.

公开(公告)号：US09379705B2

公开(公告)日：2016-06-28

申请号：US14624646

申请日：2015-02-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dal-Hee Lee ,  Jae-Woo Seo ,  Min-Ho Park

IPC: H03K19/00 ,  H03K19/0185 ,  H03K19/0944 ,  G06F17/50

CPC classification number: H03K19/0013 ,  G06F17/5072 ,  H03K19/018507 ,  H03K19/018521 ,  H03K19/0944

Abstract: An integrated circuit (IC) includes at least one unit cell. The at least one unit cell includes a first bit circuit configured to process a first bit signal, a second bit circuit configured to process a second bit signal, a first well spaced apart from boundaries of the at least one unit cell and biased to a first voltage, and a second well biased to a second voltage that is different from the first voltage. Each of the first and second bit circuits includes at least one transistor from among a plurality of transistors disposed in the first well.

Abstract translation: 集成电路（IC）包括至少一个单元电池。 所述至少一个单元单元包括被配置为处理第一位信号的第一位电路，被配置为处理第二位信号的第二位电路，与所述至少一个单位单元的边界间隔开的第一阱，并被偏置到第一位 电压，第二阱偏压到不同于第一电压的第二电压。 第一和第二位电路中的每一个包括设置在第一阱中的多个晶体管中的至少一个晶体管。