公开(公告)号：US11557720B2

公开(公告)日：2023-01-17

申请号：US17110524

申请日：2020-12-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwan Lee ,  Yongseok Kim ,  Kohji Kanamori ,  Unghwan Pi ,  Hyuncheol Kim ,  Sungwon Yoo ,  Jaeho Hong

IPC: H01L43/08 ,  H01L27/22 ,  H01L43/10 ,  G11C11/16 ,  H01L23/522 ,  H01L43/02

Abstract: A memory device includes a magnetic track layer extending on a substrate, the magnetic track layer having a folded structure that is two-dimensionally villi-shaped, a plurality of reading units including a plurality of fixed layers and a tunnel barrier layer between the magnetic track layer and each of the plurality of fixed layers, and a plurality of bit lines extending on different ones of the plurality of reading units, the plurality of reading units being between the magnetic track layer and corresponding ones of the plurality of bit lines.

公开(公告)号：US11322544B2

公开(公告)日：2022-05-03

申请号：US16734937

申请日：2020-01-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwan Lee ,  Yongseok Kim ,  Taehun Kim ,  Seokhan Park ,  Satoru Yamada ,  Jaeho Hong

IPC: H01L27/24 ,  G11C16/10 ,  G11C16/26 ,  G11C13/00 ,  H01L45/00 ,  H01L27/11524 ,  H01L27/1157

Abstract: A vertical semiconductor device includes: a channel on a substrate, the channel extending in a first direction substantially perpendicular to an upper surface of the substrate; a first data storage structure contacting a first sidewall of the channel; a second data storage structure on a second sidewall of the channel; and gate patterns on a surface of the second data storage structure, wherein the gate patterns are spaced apart from each other in the first direction, and the gate patterns extend in a second direction substantially parallel to the upper surface of the substrate.

公开(公告)号：US20220028975A1

公开(公告)日：2022-01-27

申请号：US17225716

申请日：2021-04-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwan Lee ,  Yongseok Kim ,  Hyuncheol Kim ,  Sungwon Yoo ,  Jaeho Hong

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/786

Abstract: A semiconductor device includes a gate electrode on a substrate, a channel surrounding sidewalls of the gate electrode on the substrate, and source/drain electrodes on the substrate at opposite sides of the gate electrode in a first direction parallel to an upper surface of the substrate. A thickness of the channel from the gate electrode to the source/drain electrodes in a horizontal direction parallel to the upper surface of the substrate is not constant but varies in a vertical direction perpendicular to the upper surface of the substrate.

公开(公告)号：US10312243B2

公开(公告)日：2019-06-04

申请号：US15920628

申请日：2018-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-jung Lee ,  Dongsoo Woo ,  Jin-Seong Lee ,  Namho Jeon ,  Jaeho Hong

IPC: H01L29/43 ,  H01L29/49 ,  H01L27/108 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/51

Abstract: A semiconductor memory device includes a separation member defining active regions of a substrate. Gate lines intersect the active regions and are each buried in a trench formed in the substrate. Each of the gate lines includes a lower electrode structure and an upper electrode structure on the lower electrode structure. The upper electrode structure includes a source layer substantially covering a sidewall of the trench and including a work-function adjustment element. A conductive layer is on the source layer. A work-function adjustment layer is disposed between the source layer and the conductive layer. The work-function adjustment layer includes a material different from that of the source layer and is doped with the work-function adjustment element.

公开(公告)号：US20190115351A1

公开(公告)日：2019-04-18

申请号：US15966554

申请日：2018-04-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： NAMHO JEON ,  Jin-Seong LEE ,  Hyun-jung LEE ,  Dongsoo Woo ,  Donggyu HEO ,  Jaeho Hong

IPC: H01L27/105 ,  H01L21/8239 ,  H01L21/8238 ,  H01L29/06

Abstract: Disclosed are a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a device isolation layer defining active regions of a substrate, and gate lines buried in the substrate and extending across the active regions. Each of the gate lines includes a conductive layer, a liner layer disposed between and separating the conductive layer and the substrate, and a first work function adjusting layer disposed on the conductive layer and the liner layer. The first work function adjusting layer includes a first work function adjusting material. A work function of the first work function adjusting layer is less than those of the conductive layer and the liner layer.