公开(公告)号：US10804466B2

公开(公告)日：2020-10-13

申请号：US16743594

申请日：2020-01-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-Hyun Jeong ,  Jin-Woo Lee ,  Gwan-Hyeob Koh ,  Dae-Hwan Kang

IPC: H01L45/00 ,  H01L27/24

Abstract: Provided are a memory device and a method of manufacturing the same. Memory cells of the memory device are formed separately from first electrode lines and second electrode lines, wherein the second electrode lines over the memory cells are formed by a damascene process, thereby avoiding complications associated with CMP being excessively or insufficiently performed on an insulation layer over the memory cells.

公开(公告)号：US09269746B2

公开(公告)日：2016-02-23

申请号：US14323301

申请日：2014-07-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Woo Lee ,  Youn-Seon Kang ,  Jung-Moo Lee ,  Seung-Jae Jung ,  Hyun-Su Ju

IPC: H01L45/00 ,  H01L47/00 ,  H01L29/02 ,  H01L27/24

CPC classification number: H01L27/2409 ,  H01L27/2463 ,  H01L27/2481 ,  H01L27/249 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/142 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1616 ,  H01L45/1675

Abstract: A semiconductor device includes a first electrode on a substrate, a selection device pattern, a variable resistance layer pattern, a first protective layer pattern, a second protective layer pattern and a second electrode. The selection device pattern is wider, in a given direction, than the variable resistance layer pattern. The first protective layer pattern is formed on a first pair of opposite sides of the variable resistance layer pattern. The second protective layer pattern is formed on a second pair of opposite of the variable resistance layer pattern. The second electrode is disposed on the variable resistance layer pattern.

公开(公告)号：US08759763B2

公开(公告)日：2014-06-24

申请号：US13680347

申请日：2012-11-19

Applicant: Samsung Electronics Co., Ltd

Inventor： Young-Hoon Sohn ,  Jin-Woo Lee ,  Yong-Deok Jeong ,  Yu-Sin Yang ,  Sang-Kil Lee ,  Chung-Sam Jun

IPC: G01B15/00 ,  G01N23/225 ,  H01J37/26

CPC classification number: G01B15/00 ,  G01N23/225 ,  G06T7/60 ,  G06T2207/10061 ,  H01J37/222 ,  H01J37/26 ,  H01J37/28 ,  H01J2237/24578 ,  H01J2237/2815 ,  H01J2237/2817

Abstract: A method of measuring a step height of a device using a scanning electron microscope (SEM), the method may include providing a device which comprises a first region and a second region, wherein a step is formed between the first region and the second region, obtaining a SEM image of the device by photographing the device using a SEM, wherein the SEM image comprises a first SEM image region for the first region and a second SEM image region for the second region, converting the SEM image into a gray-level histogram and calculating a first peak value related to the first SEM image region and a second peak value related to the second SEM image region, wherein the first peak value and the second peak value are repeatedly calculated by varying a focal length of the SEM, and determining a height of the step by analyzing a trend of changes in the first peak value according to changes in the focal length and a trend of changes in the second peak value according to the changes in the focal length.

Abstract translation: 使用扫描电子显微镜（SEM）测量器件的台阶高度的方法可以包括提供包括第一区域和第二区域的器件，其中在第一区域和第二区域之间形成台阶， 通过使用SEM拍摄该装置来获得该装置的SEM图像，其中，SEM图像包括用于第一区域的第一SEM图像区域和用于第二区域的第二SEM图像区域，将SEM图像转换为灰度级直方图 以及计算与第一SEM图像区域相关的第一峰值和与第二SEM图像区域相关的第二峰值，其中通过改变SEM的焦距来重复计算第一峰值和第二峰值，并且确定 通过根据焦距的变化分析第一峰值的变化趋势和根据焦距变化的第二峰值变化的趋势的步骤的高度 th。

公开(公告)号：US20140070291A1

公开(公告)日：2014-03-13

申请号：US13957121

申请日：2013-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Yong Song ,  Seung-Ho Kim ,  Ja-Young Lee ,  Jin-Woo Lee ,  Hyun-Mi Ji

IPC: H01L27/088 ,  H01L29/66

CPC classification number: H01L27/088 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823481 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10844 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/66666

Abstract: Semiconductor devices are provided. The semiconductor devices may include an isolation pattern and first, second, and third active regions of a substrate. The first active region may be spaced apart from the second active region by a first width of the isolation pattern in a direction. A gate structure may be between the first and second active regions and may include a second width wider than the first width of the isolation pattern in the direction. Related methods of forming semiconductor devices are also provided.

Abstract translation: 提供半导体器件。 半导体器件可以包括衬底的隔离图案和第一，第二和第三有源区域。 第一有源区可以沿着一个方向与隔离图案的第一宽度与第二有源区间隔开。 栅极结构可以在第一和第二有源区之间，并且可以包括比隔离图案在该方向上的第一宽度宽的第二宽度。 还提供了形成半导体器件的相关方法。