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公开(公告)号:US09431458B2
公开(公告)日:2016-08-30
申请号:US14980247
申请日:2015-12-28
发明人: Jin-Woo Lee , Youn-Seon Kang , Jung-Moo Lee , Seung-Jae Jung , Hyun-Su Ju
CPC分类号: H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L27/249 , H01L45/04 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/1253 , H01L45/142 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/1616 , H01L45/1675
摘要: A semiconductor device includes a first electrode on a substrate, a selection device pattern, a variable resistance layer pattern, a first protective layer pattern, a second protective layer pattern and a second electrode. The selection device pattern is wider, in a given direction, than the variable resistance layer pattern. The first protective layer pattern is formed on a first pair of opposite sides of the variable resistance layer pattern. The second protective layer pattern is formed on a second pair of opposite of the variable resistance layer pattern. The second electrode is disposed on the variable resistance layer pattern.
摘要翻译: 半导体器件包括衬底上的第一电极,选择器件图案,可变电阻层图案,第一保护层图案,第二保护层图案和第二电极。 选择装置图案在给定方向上比可变电阻层图案更宽。 第一保护层图案形成在可变电阻层图案的第一对相对侧上。 第二保护层图案形成在可变电阻层图案的第二对相对的第二保护层图案上。 第二电极设置在可变电阻层图案上。
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公开(公告)号:US09269746B2
公开(公告)日:2016-02-23
申请号:US14323301
申请日:2014-07-03
发明人: Jin-Woo Lee , Youn-Seon Kang , Jung-Moo Lee , Seung-Jae Jung , Hyun-Su Ju
CPC分类号: H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L27/249 , H01L45/04 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/1253 , H01L45/142 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/1616 , H01L45/1675
摘要: A semiconductor device includes a first electrode on a substrate, a selection device pattern, a variable resistance layer pattern, a first protective layer pattern, a second protective layer pattern and a second electrode. The selection device pattern is wider, in a given direction, than the variable resistance layer pattern. The first protective layer pattern is formed on a first pair of opposite sides of the variable resistance layer pattern. The second protective layer pattern is formed on a second pair of opposite of the variable resistance layer pattern. The second electrode is disposed on the variable resistance layer pattern.
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公开(公告)号:US09184218B2
公开(公告)日:2015-11-10
申请号:US14506005
申请日:2014-10-03
发明人: Lijie Zhang , Young-Bae Kim , Youn-Seon Kang , In-Gyu Baek , Masayuki Terai
CPC分类号: H01L27/249 , H01L27/2454 , H01L45/04 , H01L45/1226 , H01L45/146
摘要: A semiconductor memory device includes pillars extending upright on a substrate in a direction perpendicular to the substrate, a stack disposed on the substrate and constituted by a first interlayer insulating layer, a first conductive layer, a second interlayer insulating layer, and a second conductive layer, a variable resistance layer interposed between the pillars and the first conductive layer, and an insulating layer interposed between the first pillars and the second conductive layer.
摘要翻译: 半导体存储器件包括在垂直于衬底的方向上在衬底上直立延伸的柱,设置在衬底上并由第一层间绝缘层,第一导电层,第二层间绝缘层和第二导电层 插入在所述柱和所述第一导电层之间的可变电阻层以及插在所述第一柱和所述第二导电层之间的绝缘层。
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公开(公告)号:US10276793B2
公开(公告)日:2019-04-30
申请号:US15595307
申请日:2017-05-15
发明人: Seung-Jae Jung , Youn-Seon Kang
摘要: A variable resistance memory device includes a plurality of first conductive lines, each of the first conductive lines extends in a first direction, a plurality of second conductive lines are above the first conductive lines, and each of the second conductive lines extend in a second direction transverse to the first direction. A plurality of first memory cells are at intersections where the first and second conductive lines overlap each other, each of the first memory cells including a first variable resistance structure having a first variable resistance pattern, a first sacrificial pattern and a second variable resistance pattern sequentially stacked in the first direction on a first plane. A plurality of third conductive lines are above the second conductive lines, each of the third conductive lines extend in the first direction, and a plurality of second memory cells are at intersections where the second and the third conductive lines overlap each other. Each of the second memory cells includes a second variable resistance structure having a third variable resistance pattern, a second sacrificial pattern and a fourth variable resistance pattern sequentially stacked in the first direction on second plane.
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公开(公告)号:US09391269B2
公开(公告)日:2016-07-12
申请号:US14457439
申请日:2014-08-12
发明人: Jung-Moo Lee , Youn-Seon Kang , Seung-Jae Jung , Jung-Dal Choi
IPC分类号: H01L45/00 , H01L21/768 , H01L27/24 , H01L21/336 , H01L29/788 , H01L27/108
CPC分类号: H01L45/1233 , H01L27/2436 , H01L27/2481 , H01L45/04 , H01L45/08 , H01L45/1675
摘要: A variable resistance memory device includes a plurality of first conductive lines, a plurality of second conductive lines, a plurality of memory cells, a plurality of first air gaps and a plurality of second air gaps. The first conductive line extends in a first direction. The second conductive line is over the first conductive line and extends in a second direction crossing the first direction. The memory cell includes a variable resistance device. The memory cell is located at an intersection region of the first conductive line and the second conductive line. The first air gap extends in the first direction between the memory cells. The second air gap extends in the second direction between the memory cells.
摘要翻译: 可变电阻存储器件包括多个第一导线,多个第二导线,多个存储单元,多个第一气隙和多个第二气隙。 第一导线沿第一方向延伸。 第二导线在第一导线上方并且沿与第一方向交叉的第二方向延伸。 存储单元包括可变电阻器件。 存储单元位于第一导线和第二导线的交叉区域。 第一气隙在存储单元之间沿第一方向延伸。 第二气隙沿第二方向在存储单元之间延伸。
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