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    SEMICONDUCTOR MEMORY DEVICES, MEMORY SYSTEMS INCLUDING THE SAME AND METHODS OF OPERATING MEMORY SYSTEMS
    22.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES, MEMORY SYSTEMS INCLUDING THE SAME AND METHODS OF OPERATING MEMORY SYSTEMS 有权

    公开(公告)号：US20220121518A1

    公开(公告)日：2022-04-21

    申请号：US17562505

    申请日：2021-12-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hoi-Ju Chung ,  Sang-Uhn Cha ,  Ho-Young Song ,  Hyun-Joong Kim

    IPC: G06F11/10 ,  G11C29/52 ,  G06F3/06

    Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.

    Semiconductor memory devices, memory systems and methods of operating semiconductor memory devices
    27.
    发明授权
    Semiconductor memory devices, memory systems and methods of operating semiconductor memory devices 有权

    公开(公告)号：US10698763B2

    公开(公告)日：2020-06-30

    申请号：US16177497

    申请日：2018-11-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Uhn Cha

    IPC: G06F11/10 ,  H03M13/15

    Abstract: A semiconductor memory device is provided. The device includes a memory cell array including a plurality of dynamic memory cells; an error correction code (ECC) engine; an input/output (I/O) gating circuit connected between the ECC engine and the memory cell array; an error information register configured to store an error address and a first syndrome, the error address and the first syndrome being associated with a first error bit in a first codeword stored in a first page of the memory cell array; and a control logic configured to, based on the first codeword being read again and including a second error bit which is different from the first error bit, recover a second syndrome associated with the second error bit by using the first syndrome stored in the error information register and sequentially correct the first error bit and the second error bit.

    Semiconductor semiconductor memory devices, memory systems and methods of operating memory devices
    28.
    发明授权
    Semiconductor semiconductor memory devices, memory systems and methods of operating memory devices 有权

    公开(公告)号：US10586584B2

    公开(公告)日：2020-03-10

    申请号：US16228518

    申请日：2018-12-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang-Uhn Cha ,  Hyun-Gi Kim ,  Hoon Sin ,  Ye-Sin Ryu ,  In-Woo Jun

    IPC: G11C7/00 ,  G11C11/406 ,  G06F11/10

    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.

    Semiconductor memory devices and methods of operating the same
    29.
    发明授权
    Semiconductor memory devices and methods of operating the same 有权

    公开(公告)号：US10156995B2

    公开(公告)日：2018-12-18

    申请号：US15398409

    申请日：2017-01-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Uhn Cha ,  Hoi-Ju Chung ,  Ye-Sin Ryu ,  Seong-Jin Cho

    IPC: G06F3/06 ,  H03M13/15 ,  G11C29/52 ,  G11C11/16 ,  G06F11/10 ,  H03M13/00 ,  G11C29/00 ,  G11C29/04

    Abstract: A semiconductor memory device includes a memory cell array, a control logic circuit, and an error correction circuit. The control logic circuit generates control signals by decoding a command. The control logic circuit, in a write mode of the semiconductor memory device, controls the error correction circuit to read a first unit of data from a selected sub-page and to generate a first parity data based on one of the first sub unit of data and the second sub unit of data and a main data to be written into the sub-page while generating syndrome data by performing an error correction code decoding on the first unit of data. The error correction circuit, when a first sub unit of data includes at least one error bit, selectively modifies the first parity data based on a data mask signal associated with the main data.

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