公开(公告)号：US12224336B2

公开(公告)日：2025-02-11

申请号：US18088550

申请日：2022-12-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungchan Yun ,  Donghwan Han

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/84

Abstract: A semiconductor device including: a first structure including: a first semiconductor pattern protruding from a substrate, the first semiconductor pattern being a channel; a first conductive pattern surrounding the first semiconductor pattern, the first conductive pattern being a gate electrode; a first impurity region under the first semiconductor pattern, the first impurity region contacting the first semiconductor pattern, the first impurity region being a source or drain region; and a second impurity region contacting the first semiconductor pattern, the second impurity region being the other of the source or drain region; and a second structure including: second semiconductor patterns spaced apart from each other, each of the second semiconductor patterns protruding from the substrate; second conductive patterns surrounding the second semiconductor patterns, respectively; and first contact plugs connected to the second conductive patterns, wherein the first structure is a vfet, and the second structure includes a resistor or a capacitor.

公开(公告)号：US12183786B2

公开(公告)日：2024-12-31

申请号：US17536939

申请日：2021-11-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak Hong ,  Seungchan Yun ,  Kang-ill Seo

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A multi-stack semiconductor device includes: a substrate; a multi-stack transistor formed on the substrate and including a nanosheet transistor and a fin field-effect transistor (FinFET) above the nanosheet transistor, wherein the nanosheet transistor includes a plurality nanosheet layers surrounded by a lower gate structure except between the nanosheet layers, the FinFET includes at least one fin structure, of which at least top and side surfaces are surrounded by an upper gate structure, and each of the lower and upper gate structures includes: a gate oxide layer formed on the nanosheet layers and the at least one fin structure; and a gate metal pattern formed on the gate oxide layer. At least one of the lower and upper gate structures includes an extra gate (EG) oxide layer formed between the gate oxide layer and the nanosheet layers and/or between the gate oxide layer and the at least one fin structure.

公开(公告)号：US20230317824A1

公开(公告)日：2023-10-05

申请号：US18329206

申请日：2023-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungchan Yun ,  Donghwan Han

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/6656 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/7851 ,  H01L29/7855 ,  H01L2029/7858

Abstract: A semiconductor device including a substrate including first and second regions, a first transistor on the first region and including a first semiconductor pattern protruding from the first region; a first gate structure covering an upper surface and sidewall of the first semiconductor pattern; first source/drain layers on the first semiconductor pattern at opposite sides of the first gate structure, upper surfaces of the first source/drain layers being closer to the substrate than an uppermost surface of the first gate structure; and a second transistor on the second region and including a second semiconductor pattern protruding from the second region; a second gate structure covering a sidewall of the second semiconductor pattern; and a second source/drain layer under the second semiconductor pattern; and a third source/drain layer on the second semiconductor pattern, wherein the upper surface of the first region is lower than the upper surface of the second region.

公开(公告)号：US11670701B2

公开(公告)日：2023-06-06

申请号：US17019767

申请日：2020-09-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungchan Yun ,  Donghwan Han

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/6656 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/7851 ,  H01L29/7855 ,  H01L2029/7858

Abstract: A semiconductor device including a substrate including first and second regions, a first transistor on the first region and including a first semiconductor pattern protruding from the first region; a first gate structure covering an upper surface and sidewall of the first semiconductor pattern; first source/drain layers on the first semiconductor pattern at opposite sides of the first gate structure, upper surfaces of the first source/drain layers being closer to the substrate than an uppermost surface of the first gate structure; and a second transistor on the second region and including a second semiconductor pattern protruding from the second region; a second gate structure covering a sidewall of the second semiconductor pattern; and a second source/drain layer under the second semiconductor pattern; and a third source/drain layer on the second semiconductor pattern, wherein the upper surface of the first region is lower than the upper surface of the second region.

公开(公告)号：US20230163202A1

公开(公告)日：2023-05-25

申请号：US18094597

申请日：2023-01-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehong LEE ,  Seungchan Yun ,  Sooyoung Park ,  Kang-ill Seo

IPC: H01L29/73 ,  H01L29/786 ,  H01L23/48 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7302 ,  H01L29/78696 ,  H01L23/481 ,  H01L29/0673 ,  H01L29/66265

Abstract: Provided is field-effect transistor structure including: a substrate including therein at least one 1st doped region, a 2nd doped region on one side of the 1st doped region, and a 3rd doped region on another side of the 1st doped region; a 1st channel structure including therein a 4th doped region on the 2nd doped region in the substrate; and a 2nd channel structure, at a side of the 1st channel structure, including therein a 5th doped region on the 3rd doped region in the substrate, wherein the 4th, 2nd, 1st, 3rd and 5th doped regions form a sequentially connected passive device.

公开(公告)号：US20230129233A1

公开(公告)日：2023-04-27

申请号：US18088550

申请日：2022-12-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungchan Yun ,  Donghwan Han

IPC: H01L29/66 ,  H01L29/78

Abstract: A semiconductor device including: a first structure including: a first semiconductor pattern protruding from a substrate, the first semiconductor pattern being a channel; a first conductive pattern surrounding the first semiconductor pattern, the first conductive pattern being a gate electrode; a first impurity region under the first semiconductor pattern, the first impurity region contacting the first semiconductor pattern, the first impurity region being a source or drain region; and a second impurity region contacting the first semiconductor pattern, the second impurity region being the other of the source or drain region; and a second structure including: second semiconductor patterns spaced apart from each other, each of the second semiconductor patterns protruding from the substrate; second conductive patterns surrounding the second semiconductor patterns, respectively; and first contact plugs connected to the second conductive patterns, wherein the first structure is a vfet, and the second structure includes a resistor or a capacitor.

公开(公告)号：US20230045681A1

公开(公告)日：2023-02-09

申请号：US17967950

申请日：2022-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghwan Han ,  Seungchan Yun

IPC: H01L29/78 ,  H01L27/092 ,  H01L27/12 ,  H01L21/8238 ,  H01L29/08

Abstract: A semiconductor device includes a substrate including an active region that extends in a first direction; a gate structure that intersects the active region and that extends in a second direction; a source/drain region on the active region on at least one side of the gate structure; a contact plug on the source/drain region on the at least one side of the gate structure; and a contact insulating layer on sidewalls of the contact plug, wherein a lower end of the contact plug is closer to the substrate than a lower end of the source/drain region.

公开(公告)号：US20210193818A1

公开(公告)日：2021-06-24

申请号：US17019767

申请日：2020-09-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungchan Yun ,  Donghwan Han

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

Abstract: A semiconductor device including a substrate including first and second regions, a first transistor on the first region and including a first semiconductor pattern protruding from the first region; a first gate structure covering an upper surface and sidewall of the first semiconductor pattern; first source/drain layers on the first semiconductor pattern at opposite sides of the first gate structure, upper surfaces of the first source/drain layers being closer to the substrate than an uppermost surface of the first gate structure; and a second transistor on the second region and including a second semiconductor pattern protruding from the second region; a second gate structure covering a sidewall of the second semiconductor pattern; and a second source/drain layer under the second semiconductor pattern; and a third source/drain layer on the second semiconductor pattern, wherein the upper surface of the first region is lower than the upper surface of the second region.

公开(公告)号：US20250159980A1

公开(公告)日：2025-05-15

申请号：US18758376

申请日：2024-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungchan Yun ,  Panjae Park ,  Kang-ill Seo

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Stacked field-effect transistor (FET) devices are provided. A stacked FET device includes a lower FET having lower channel layers and a lower gate material that is between the lower channel layers. The stacked FET device includes an upper FET that is on the lower FET. The upper FET has upper channel layers and an upper gate material that is between the upper channel layers. Moreover, the stacked FET device includes an insulating layer that is between the lower gate material and the upper gate material and not in a region in which the lower channel layers are overlapped by the upper channel layers. Related methods of forming stacked FET devices are also provided.

公开(公告)号：US20250040242A1

公开(公告)日：2025-01-30

申请号：US18521323

申请日：2023-11-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Keumseok Park ,  Seungchan Yun ,  Kang-ill Seo

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: Provided is a semiconductor device which includes: a 1st source/drain region connected to a 1st channel structure which is controlled by a 1st gate structure; a 2nd source/drain region, above the 1st source/drain region, connected to a 2nd channel structure which is controlled by a 2nd gate structure; and a middle isolation structure between the 1st gate structure and the 2nd gate structure, wherein the middle isolation structure comprises two or more vertically-stacked semiconductor layers.