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    PROCESSING DEVICE BASED ON MAGNETIC TUNNEL JUNCTION (MTJ) ELEMENT AND ELECTRONIC SYSTEM INCLUDING THE PROCESSING DEVICE
    21.
    发明申请
    PROCESSING DEVICE BASED ON MAGNETIC TUNNEL JUNCTION (MTJ) ELEMENT AND ELECTRONIC SYSTEM INCLUDING THE PROCESSING DEVICE 有权

    公开(公告)号：US20220261625A1

    公开(公告)日：2022-08-18

    申请号：US17474466

    申请日：2021-09-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kangho LEE ,  Boyoung SEO ,  Sangjoon KIM ,  Seungchul JUNG

    IPC: G06N3/063 ,  G11C11/16

    Abstract: Provided is a processing device having improved reliability and power consumption efficiency of analog calculations as well as high cost efficiency due to reduction in a size of a bit-cell, and an electronic system including the processing device. The processing device includes: at least one bit-cell line on which a plurality of bit-cells are connected to each other in series, wherein each of the bit-cells includes: a first magnetic tunnel junction (MTJ) element; a second MTJ element connected to the first MTJ element in parallel; a first switching element connected to the first MTJ element in series; and a second switching element connected to the second MTJ element in series, and wherein on the bit-cell line, two adjacent bit-cells are connected to each other in series in a mirroring structure.

    METHOD AND COMPUTING DEVICE WITH A MULTIPLIER-ACCUMULATOR CIRCUIT
    23.
    发明申请
    METHOD AND COMPUTING DEVICE WITH A MULTIPLIER-ACCUMULATOR CIRCUIT 有权

    公开(公告)号：US20210064367A1

    公开(公告)日：2021-03-04

    申请号：US16987863

    申请日：2020-08-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang Joon KIM ,  Seungchul JUNG

    IPC: G06F9/30 ,  G04F10/00 ,  H03K21/08

    Abstract: Provided is a multiplier-accumulator (MAC) system, circuit, and method. The MAC system includes a MAC circuit, including a plurality of resistors, having respective resistances, a capacitor connected to the plurality of resistors to charge, in response to a plurality of input signals, the capacitor with electric charge, and a time-to-digital converter (TDC) configured to convert information of a charge time of the capacitor, due to the electric charge, into a digital value, wherein the digital value is an accumulation result of the MAC circuit.

    STIMULATOR AND METHOD OF CONTROLLING STIMULATOR
    25.
    发明申请
    STIMULATOR AND METHOD OF CONTROLLING STIMULATOR 审中-公开

    公开(公告)号：US20180133471A1

    公开(公告)日：2018-05-17

    申请号：US15789552

    申请日：2017-10-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyungwoo LEE ,  JongPal KIM ,  Seungchul JUNG

    IPC: A61N1/36

    Abstract: A stimulator and a method of controlling the stimulator are provided. The method includes determining a waveform of a stimulus signal for a target, based on biological feedback of the target responding to a first stimulus signal, calculating a bioimpedance of the target based on a voltage waveform measured by applying the stimulus signal with the determined waveform to the target, and determining an operating voltage of the stimulator based on the determined waveform and the calculated bioimpedance.

    DEVICE AND METHOD WITH COMPUTATIONAL MEMORY
    27.
    发明公开
    DEVICE AND METHOD WITH COMPUTATIONAL MEMORY 审中-公开

    公开(公告)号：US20240112708A1

    公开(公告)日：2024-04-04

    申请号：US18108737

    申请日：2023-02-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyungwoo LEE ,  Soon-Wan KWON ,  Seungchul JUNG

    IPC: G11C7/10 ,  G06F7/544 ,  G11C7/12 ,  G11C11/54

    CPC classification number: G11C7/1084 ,  G06F7/5443 ,  G11C7/12 ,  G11C11/54

    Abstract: A computational memory device and a method using the computational memory device are provided. The computational memory device includes memory banks configured to store weight data of a neural network model and a weight memory block configured to provide at least some of the weight data from memory banks in response to a weight request, a computational memory block physically stacked on the weight memory block such faces of the respective blocks face each other, the computational memory block configured to perform a multiply-accumulate (MAC) operation between the at least some of the weight data and at least some of input data by using a bit cell array including bit cells, and a communication interface configured to perform communication between the weight memory block and the computational memory block.

    MEMORY AND METHOD WITH IN-MEMORY COMPUTING DEFECT DETECTION
    28.
    发明公开
    MEMORY AND METHOD WITH IN-MEMORY COMPUTING DEFECT DETECTION 审中-公开

    公开(公告)号：US20240071548A1

    公开(公告)日：2024-02-29

    申请号：US18091258

    申请日：2022-12-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sungmeen MYUNG ,  Seok Ju YUN ,  Jaehyuk LEE ,  Seungchul JUNG

    IPC: G11C29/36 ,  G11C29/00 ,  G11C29/44

    CPC classification number: G11C29/36 ,  G11C29/44 ,  G11C29/785 ,  G11C2029/3602

    Abstract: A method and memory device with in-memory computing defection detection is disclosed. A memory device includes a memory including banks, wherein each bank includes a respective plurality of bit-cells, an in-memory computation (IMC) operator configured to perform an IMC operation between first data while the first data is in the bit-cells of the memory and second data received as input to the memory device, wherein the banks share the operator, and wherein the memory device is configured to: generate a first test pattern that is stored in the memory and generate a second test pattern applied to the IMC operator, and based thereon determine whether a defect has occurred in either the memory or the operator, and perform a repair based on the determination that a defect has occurred.

    IN-MEMORY COMPUTING (IMC) PROCESSOR AND OPERATING METHOD OF IMC PROCESSOR
    29.
    发明公开
    IN-MEMORY COMPUTING (IMC) PROCESSOR AND OPERATING METHOD OF IMC PROCESSOR 审中-公开

    公开(公告)号：US20240061649A1

    公开(公告)日：2024-02-22

    申请号：US18306686

    申请日：2023-04-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Soon-Wan KWON ,  Seok Ju YUN ,  Seungchul JUNG

    IPC: G06F7/544 ,  G06F7/527 ,  G11C7/10

    CPC classification number: G06F7/5443 ,  G06F7/5277 ,  G11C7/1069

    Abstract: An in-memory computing (IMC) processor includes IMC macros, and includes a static random access memory (SRAM) IMC device including the plurality of IMC macros, and configured to perform a multiply and accumulate (MAC) operation between input data and first weight data of a first weight map applied to a first of IMC macros in a first direction in which an input feature map including the input data is written to the first IMC macro, and a two-dimensional (2D) shift accumulator configured to perform a shift operation on partial sums corresponding to respective MAC operation results of the IMC macros and accumulate a result of the shift operation.

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