公开(公告)号：US20230086202A1

公开(公告)日：2023-03-23

申请号：US17839675

申请日：2022-06-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Aenee Jang ,  Yoonsung Kim ,  Seungduk Baek ,  Yunrae Cho

IPC: H01L23/00 ,  H01L25/065 ,  H01L21/66

Abstract: A semiconductor package is provided. The semiconductor package includes, a base structure including a body, an upper pad on the body, and an upper insulating layer on a side surface of the upper pad, the base structure having a planar upper surface provided by the upper insulating layer and the upper pad; and a semiconductor chip on the planar upper surface of the base structure, and including a substrate, a wiring structure below the substrate, a low dielectric layer on a side surface of the wiring structure, a lower connection pad below the wiring structure, and a lower insulating layer on a side surface of the lower connection pad, the semiconductor chip having a planar lower surface provided by the lower insulating layer and the lower connection pad, a side surface provided by the lower insulating layer and the substrate, and a recess surface extending from one end of the side surface to one end of the planar lower surface, wherein the low dielectric layer is spaced apart from the recess surface of the semiconductor chip by the lower insulating layer.

公开(公告)号：US11257725B2

公开(公告)日：2022-02-22

申请号：US17010059

申请日：2020-09-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehyeong Kim ,  Hyeongmun Kang ,  Seungduk Baek

IPC: H01L21/66 ,  H01L23/00 ,  H01L25/18

Abstract: Disclosed is a semiconductor package comprising a first semiconductor chip and at least one second semiconductor chip on the first semiconductor chip. The second semiconductor chip includes first and second test bumps that are adjacent to an edge of the second semiconductor chip and are on a bottom surface of the second semiconductor chip. The first and second test bumps are adjacent to each other. The second semiconductor chip also includes a plurality of data bumps that are adjacent to a center of the second semiconductor chip and are on the bottom surface of the second semiconductor chip. A first interval between the second test bump and one of the data bumps is greater than a second interval between the first test bump and the second test bump. The one of the data bumps is most adjacent to the second test bump.

公开(公告)号：US20210005576A1

公开(公告)日：2021-01-07

申请号：US16822693

申请日：2020-03-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoungsoo Kim ,  Sunwon Kang ,  Seungduk Baek ,  Ho Geon Song ,  Kyung Suk Oh

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor package includes a first die including a signal region and a peripheral region bordering the signal region and having first vias in the peripheral region, a second die stacked on the first die and having second vias at positions corresponding to the first vias in the peripheral region, and first connection terminals between the first die and the second die that are configured to connect the second vias to the first vias, respectively. The peripheral region includes first regions and second regions configured to transmit different signals, which are alternately arranged in a first direction. The first vias are arranged in at least two rows along a second direction intersecting the first direction in each of the first and second regions.

公开(公告)号：US09165916B2

公开(公告)日：2015-10-20

申请号：US14326631

申请日：2014-07-09

Applicant: Samsung Electronics Co., Ltd

Inventor： Hyunsoo Chung ,  Seungduk Baek ,  In-Young Lee ,  Tae-Je Cho

IPC: H01L21/44 ,  H01L21/48 ,  H01L25/00 ,  H01L25/065 ,  H01L23/48 ,  H01L23/29 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/50 ,  H01L21/563 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2224/83 ,  H01L2924/00

Abstract: A semiconductor package and a method of fabricating the same. The method may include mounting a lower stack including a plurality of lower semiconductor chips on a substrate and mounting an upper stack including a plurality of upper semiconductor chips on the lower stack. According to example embodiments of the inventive concept, the semiconductor package can be easily fabricated.

Abstract translation: 一种半导体封装及其制造方法。 该方法可以包括将包括多个下半导体芯片的下堆叠安装在基板上，并且在下堆叠上安装包括多个上半导体芯片的上堆叠。 根据本发明构思的示例实施例，可以容易地制造半导体封装。