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    Substrate assembly semiconductor package including the same and method of manufacturing the semiconductor package
    1.
    发明授权
    Substrate assembly semiconductor package including the same and method of manufacturing the semiconductor package 有权

    公开(公告)号：US10861826B2

    公开(公告)日：2020-12-08

    申请号：US16385363

    申请日：2019-04-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyung Suk Oh ,  Do-Hyun Kim ,  Sunwon Kang

    IPC: H01L23/48 ,  H01L29/40 ,  H01L25/065 ,  H01L25/00

    Abstract: A semiconductor package includes a substrate, a first semiconductor chip on the substrate, a second semiconductor chip on the first semiconductor chip and a connection structure. The second semiconductor chip includes a first segment that protrudes outwardly beyond one side of the first semiconductor chip and a second connection pad on a bottom surface of the first segment of the second semiconductor chip. The connection structure includes a first structure between the substrate and the first segment of the second semiconductor chip and a first columnar conductor penetrating the first structure to be in contact with the substrate and being disposed between the second connection pad and the substrate, thereby electrically connecting the second semiconductor chip to the substrate.

    SEMICONDUCTOR PACKAGE
    4.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20210005576A1

    公开(公告)日：2021-01-07

    申请号：US16822693

    申请日：2020-03-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyoungsoo Kim ,  Sunwon Kang ,  Seungduk Baek ,  Ho Geon Song ,  Kyung Suk Oh

    IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

    Abstract: A semiconductor package includes a first die including a signal region and a peripheral region bordering the signal region and having first vias in the peripheral region, a second die stacked on the first die and having second vias at positions corresponding to the first vias in the peripheral region, and first connection terminals between the first die and the second die that are configured to connect the second vias to the first vias, respectively. The peripheral region includes first regions and second regions configured to transmit different signals, which are alternately arranged in a first direction. The first vias are arranged in at least two rows along a second direction intersecting the first direction in each of the first and second regions.

    Semiconductor package
    6.
    发明授权
    Semiconductor package 有权

    公开(公告)号：US11495576B2

    公开(公告)日：2022-11-08

    申请号：US16822693

    申请日：2020-03-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyoungsoo Kim ,  Sunwon Kang ,  Seungduk Baek ,  Ho Geon Song ,  Kyung Suk Oh

    IPC: H01L23/498 ,  H01L23/48 ,  H01L23/544 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00

    Abstract: A semiconductor package includes a first die including a signal region and a peripheral region bordering the signal region and having first vias in the peripheral region, a second die stacked on the first die and having second vias at positions corresponding to the first vias in the peripheral region, and first connection terminals between the first die and the second die that are configured to connect the second vias to the first vias, respectively. The peripheral region includes first regions and second regions configured to transmit different signals, which are alternately arranged in a first direction. The first vias are arranged in at least two rows along a second direction intersecting the first direction in each of the first and second regions.

    Semiconductor package
    7.
    发明授权
    Semiconductor package 有权

    公开(公告)号：US12165974B2

    公开(公告)日：2024-12-10

    申请号：US17392936

    申请日：2021-08-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Won-Young Kim ,  Sunwon Kang

    IPC: H01L23/31 ,  H01L23/00 ,  H01L23/528 ,  H01L23/538 ,  H01L25/065

    Abstract: Disclosed is a semiconductor package including a semiconductor chip that includes a chip pad on one surface of the semiconductor chip, a redistribution pattern on the one surface of the semiconductor chip and electrically connected to the chip pad, and a photosensitive dielectric layer between the semiconductor chip and the redistribution pattern. The photosensitive dielectric layer may be in physical contact with the redistribution pattern. The redistribution pattern includes a signal redistribution pattern, a ground redistribution pattern, and a power redistribution pattern. A vertical distance between the chip pad and the signal redistribution pattern may be greater than a width of the signal redistribution pattern.

    SEMICONDUCTOR PACKAGE STRUCTURE AND SEMICONDUCTOR MODULE INCLUDING THE SAME
    8.
    发明申请
    SEMICONDUCTOR PACKAGE STRUCTURE AND SEMICONDUCTOR MODULE INCLUDING THE SAME 审中-公开

    公开(公告)号：US20190164870A1

    公开(公告)日：2019-05-30

    申请号：US16029770

    申请日：2018-07-09

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： YoungJoon Lee ,  Sunwon Kang

    IPC: H01L23/495 ,  H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31

    Abstract: Disclosed are semiconductor package structure and semiconductor modules including the same. The semiconductor module includes a circuit board, a first semiconductor package over the circuit board, and a connection structure on the circuit board and connecting the circuit board and the first semiconductor package. The first semiconductor package includes a first package substrate. A difference in coefficient of thermal expansion between the connection structure and the circuit board may be less than a difference in coefficient of thermal expansion between the circuit board and the first package substrate.

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