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公开(公告)号:US09785493B1
公开(公告)日:2017-10-10
申请号:US15373887
申请日:2016-12-09
发明人: Zhengyi Zhang , Yingda Dong
CPC分类号: G11C16/3427 , G06F11/1048 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0466 , G11C16/0483 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3431 , G11C16/3445 , G11C16/3459 , G11C16/3481 , G11C16/349 , G11C29/025 , G11C29/028 , G11C29/42 , G11C29/44 , G11C29/52 , G11C2029/0409
摘要: A memory device and associated techniques provide a read recovery of data in case of a short circuit between word lines. When cells of a recovery word line WLrec are successfully programmed but cells of an adjacent work line WLrec+1 are not successfully programmed, the data of the cells of WLrec can be recovered. The cells of WLrec+1 are erased so that a low pass voltage on WLrec+1 is adequate to provide these cells in a conductive state during the recovery read of WLrec. Capacitive coupling between the word lines which shifts the apparent threshold voltage of the cells on WLrec is reduced so that a more accurate recovery read can be performed. Read voltages on WLrec can be upshifted compared to baseline read voltages.