公开(公告)号：US08279912B2

公开(公告)日：2012-10-02

申请号：US11373928

申请日：2006-03-13

申请人： Dariush Dabiri ,  Jose Tellado ,  Sandeep Kumar Gupta

发明人： Dariush Dabiri ,  Jose Tellado ,  Sandeep Kumar Gupta

IPC分类号： H04B1/38 ,  H04B1/40 ,  H03K9/00

CPC分类号： H04L5/1423 ,  H04B3/23

摘要： Embodiments of a method and apparatus for reducing non-linear transmit signal components of a receive signal of a transceiver signal are disclosed. The method includes the transceiver simultaneously transmitting a transmit signal, and receiving the receive signal. A non-linear replica signal of non-linear transmission signal components that are created in the transceiver by a transmit signal DAC, and imposed onto the receive signal, is generated. The non-linear replica signal is subtracted from the received signal reducing the non-linear transmission signal components imposed onto the receive signal.

摘要翻译： 公开了一种用于减少收发信机的接收信号的非线性发送信号分量的方法和装置的实施例。 该方法包括收发机同时发送发送信号，并接收接收信号。 产生通过发送信号DAC在收发器中产生且施加到接收信号上的非线性传输信号分量的非线性复制信号。 从接收到的信号中减去非线性复制信号，减少施加在接收信号上的非线性传输信号分量。

公开(公告)号：US20230261659A1

公开(公告)日：2023-08-17

申请号：US17684098

申请日：2022-03-01

申请人： Sandeep Kumar Gupta

发明人： Sandeep Kumar Gupta

IPC分类号： H03K19/08 ,  H03K19/17784 ,  H03K19/20 ,  H03K19/0185

CPC分类号： H03K19/0813 ,  H03K19/17784 ,  H03K19/20 ,  H03K19/018585

摘要： Apparatuses, and methods, for digital cells power reduction are disclosed. For an embodiment, a first plurality of digital logic cells are directly connected to a Vdd terminal and a Vss terminal that have a potential difference of VDD, a second plurality of digital logic cells being directly connected to a Vdd_R terminal and a Vss_R terminal, wherein a potential difference between the Vdd_R terminal and the Vss terminal is (VDD−X1), and a potential difference between the Vss_R terminal and the Vss terminal is X2, wherein at least one digital logic cell has at least one of (a) an input connected to an output of at least one digital logic cell of the second plurality, or (b) an output connected to an input of at least one digital logic cell of the second plurality. Vdd, Vdd_R and Vss_R terminal voltages can be generated by an array of devices.

公开(公告)号：US07015842B1

公开(公告)日：2006-03-21

申请号：US11033661

申请日：2005-01-12

申请人： Sandeep Kumar Gupta ,  Oleksiy Zabroda

发明人： Sandeep Kumar Gupta ,  Oleksiy Zabroda

IPC分类号： H03M1/00

CPC分类号： G11C27/024 ,  H03M1/1215 ,  H03M1/1245

摘要： A high-speed sampling system and an analog to digital converter are disclosed. One embodiment of a method of sampling a signal includes receiving an analog signal and generating first samples at a rate of Fs, and generating second sub-samples from the first samples at a rate of Fs/N and having a relative phase of approximately (360/N)*(i−1) degrees, where i varies from 1 to N. In a first embodiment, at most two second sub-samplers are tracking the output of the first sampler at any point in time. In a second embodiment, only one of the N second sub-samplers are tracking the output of the first sampler at any point in time. A third embodiment further includes generating third samples from the second samples at a rate of Fs/N, and having a relative phase of approximately ((360/N)*(i−1)+180) degrees. A method of interleaved analog to digital converting includes corresponding time interleaved ADCs receiving the third samples.

公开(公告)号：US06529058B2

公开(公告)日：2003-03-04

申请号：US09956978

申请日：2001-09-21

申请人： Sandeep Kumar Gupta

发明人： Sandeep Kumar Gupta

IPC分类号： H03H1126

CPC分类号： H03K5/133 ,  H03K2005/00039 ,  H03K2005/0013 ,  H03K2005/00143 ,  H03K2005/00202

摘要： A circuit and method for obtaining a stable delay for a clock signal comprises a current source to generate a constant current having a first value; first and second current over capacitance (I/C) stages coupled to the current source and between a supply voltage and ground; and a capacitor, having a second value and coupled to a node formed by an output of the first I/C stage and an input of the second I/C stage. Application of a clock signal to an input of the first I/C stage produces an output at a logic gate coupled to an output of the second I/C stage. The output has a stable delay based on the first and second values. Additionally, the first and second values (i.e., the value of the current or capacitance) can be changed to achieve a desired amount of the delay applied to the input clock signal.